AM79C976 datasheet(163/309 Pages) AMD

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Am79C976

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P R E L I M INARY

PHY Access Register

Offset 0D0h

This register gives the host CPU indirect access to the

MII Management Bus (MDC/MDIO). Through this reg-

ister the host CPU can read or write any external PHY

Bus.

All bits in this register are cleared to 0 when the RST

pin is asserted. This register is not affected by the serial

EEPROM read operation or by a serial EEPROM read

error.

Table 69. PHY_ACCESS: PHY Access Register

Bit

Name

Description

PHY_CMD_DONE

PHY Command Complete. This read-only bit is set to 0 after a write access to this register and

remains 0 until the end of the MII Management Frame that is generated by the write access.

When the value of this bit is 1, the PHY_DATA field contains valid data.

PHY_WR_CMD

PHY Write Command. When this bit is set, an MII Management Frame will be sent to write the

contents of the PHY_DATA field to the external PHY register addressed by the PHY_ADDR and

PHY_REG_ADDR fields. This bit must not be set at the same time that the

PHY_BLK_RD_CMD bit or the PHY_NBLK_RD_CMD bit is set.

PHY_BLK_RD_CMD

PHY Blocking Read Command. When the bit is set, an MII Management Frame will be sent to

read the contents of the PHY_DATA field to the external PHY register addressed by the

PHY_ADDR and PHY_REG_ADDR fields. After this bit is set, the next attempt to read this

data read from the selected PHY register.

This bit must not be set at the same time that the PHY_WR_CMD bit or the

PHY_NBLK_RD_CMD bit is set.

PHY_NBLK_RD_CM

PHY Non-Blocking Read Command. When the bit is set, an MII Management Frame will be

sent to read the contents of the PHY_DATA field to the external PHY register addressed by the

PHY_ADDR and PHY_REG_ADDR fields. After this bit is set, the host CPU can read this

PHY_DATA field contains valid data read from the selected PHY register. Alternatively, the host

CPU can wait for the MCCINT interrupt (INT0, bit 17).

This bit must not be set at the same time that the PHY_WR_CMD bit or the

PHY_BLK_RD_CMD bit is set.

PHY_PRE_SUP

Preamble Suppression. If this bit is set, the MII Management Frame will be sent without a

preamble. Before setting this bit the host CPU must make sure that the external PHY

addressed by the PHY_ADDR field is capable of accepting MII Management Frames without

preambles.

RES

Reserved location. Written as zero and read as undefined.

25-21

PHY_ADDR

PHY Address. The address of the external PHY device to be accessed.

20-16

PHY_REG_ADDR

PHY Register Address. The address of the register in the external PHY device to be accessed.

15-0

PHY_DATA

PHY Data. Data written to or read from the external PHY register specified by PHY_ADDR and

PHY_REG_ADDR.

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