AD9361BBCZ datasheet(17/36 Pages) AD

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Data Sheet

AD9361

Rev. D | Page 17 of 36

Pin No.

Type1

Mnemonic

Description

AUXDAC2

Auxiliary DAC 2 Output.

TEST/ENABLE

Test Input. Ground this pin for normal operation.

C5, C6, D5, D6

CTRL_IN0 to CTRL_IN3

Control Inputs. Used for manual RX gain and TX attenuation control.

VDDA1P3_RX_RF

Receiver 1.3 V Supply Input. Connect to D3.

VDDA1P3_RX_TX

1.3 V Supply Input.

D4, E4 to E6,

F4 to F6, G4

CTRL_OUT0, CTRL_OUT1 to

CTRL_OUT3, CTRL_OUT6 to

CTRL_OUT4, CTRL_OUT7

Control Outputs. These pins are multipurpose outputs that have programmable

functionality.

I/O

P0_D9/TX_D4_P

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D9, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D4_P) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

I/O

P0_D7/TX_D3_P

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D7, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D3_P) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

I/O

P0_D5/TX_D2_P

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D5, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D2_P) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

D10

I/O

P0_D3/TX_D1_P

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D3, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D1_P) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

D11

I/O

P0_D1/TX_D0_P

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D1, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D0_P) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

D12, F7, F9,

F11, G12, H7,

H10, K12

VSSD

Digital Ground. Tie these pins directly to the VSSA analog ground on the printed

circuit board (one ground plane).

E1, F1

RX2B_P, RX2B_N

Receive Channel 2 Differential Input B. Each pin can be used as a single-ended

input or combined to make a differential pair. These inputs experience

degraded performance above 3 GHz. Tie unused pins to ground.

VDDA1P3_RX_LO

Receive LO 1.3 V Supply Input.

VDDA1P3_TX_LO_BUFFER

1.3 V Supply Input.

I/O

P0_D11/TX_D5_P

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D11, it functions as part of the 12-bit bidirectional parallel CMOS level

Data Port 0. Alternatively, this pin (TX_D5_P) can function as part of the LVDS

6-bit TX differential input bus with internal LVDS termination.

I/O

P0_D8/TX_D4_N

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D8, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D4_N) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

I/O

P0_D6/TX_D3_N

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D6, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D3_N) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

E10

I/O

P0_D4/TX_D2_N

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D4, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D2_N) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

E11

I/O

P0_D2/TX_D1_N

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D2, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D1_N) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

E12

I/O

P0_D0/TX_D0_N

Digital Data Port P0/Transmit Differential Input Bus. This is a dual function pin.

As P0_D0, it functions as part of the 12-bit bidirectional parallel CMOS level Data

Port 0. Alternatively, this pin (TX_D0_N) can function as part of the LVDS 6-bit TX

differential input bus with internal LVDS termination.

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