AD9361BBCZ datasheet(16/36 Pages) AD

16 / 36 page

AD9361

Data Sheet

Rev. D | Page 16 of 36

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration, Top View

Table 13. Pin Function Descriptions

Pin No.

Type1

Mnemonic

Description

A1, A2

RX2A_N, RX2A_P

Receive Channel 2 Differential Input A. Alternatively, each pin can be used as a

single-ended input or combined to make a differential pair. Tie unused pins to

ground.

A3, M3

No Connect. Do not connect to these pins.

A4, A6, B1, B2,

B12, C2, C7 to

C12, F3, H2,

H3, H6, J2, K2,

L2, L3, L7 to

L12, M4, M6

VSSA

Analog Ground. Tie these pins directly to the VSSD digital ground on the printed

circuit board (one ground plane).

TX_MON2

Transmit Channel 2 Power Monitor Input. If this pin is unused, tie it to ground.

A7, A8

TX2A_N, TX2A_P

Transmit Channel 2 Differential Output A. Tie unused pins to 1.3 V.

A9, A10

TX2B_N, TX2B_P

Transmit Channel 2 Differential Output B. Tie unused pins to 1.3 V.

A11

VDDA1P1_TX_VCO

Transmit VCO Supply Input. Connect to B11.

A12

TX_EXT_LO_IN

External Transmit LO Input. If this pin is unused, tie it to ground.

AUXDAC1

Auxiliary DAC 1 Output.

B4 to B7

GPO_3 to GPO_0

3.3 V Capable General-Purpose Outputs.

VDD_GPO

2.5 V to 3.3 V Supply for the AUXDAC and General-Purpose Output Pins. When

the VDD_GPO supply is not used, this supply must be set to 1.3 V.

VDDA1P3_TX_LO

Transmit LO 1.3 V Supply Input.

B10

VDDA1P3_TX_VCO_LDO

Transmit VCO LDO 1.3 V Supply Input. Connect to B9.

B11

TX_VCO_LDO_OUT

Transmit VCO LDO Output. Connect to A11 and a 1 µF bypass capacitor in series

with a 1 Ω resistor to ground.

C1, D1

RX2C_P, RX2C_N

Receive Channel 2 Differential Input C. Each pin can be used as a single-ended

input or combined to make a differential pair. These inputs experience

degraded performance above 3 GHz. Tie unused pins to ground.

RX2A_N

RX2A_P

VSSA

TX_MON2

VSSA

TX2A_N

TX2A_P

TX2B_N

TX2B_P

VDDA1P1_

TX_VCO

TX_VCO_

LDO_OUT

TX_EXT_

LO_IN

VSSA

AUXDAC1

GPO_3

GPO_2

GPO_1

GPO_0

VDD_GPO

VDDA1P3_

TX_LO

VDDA1P3_

RX_SYNTH

VDDA1P3_

TX_VCO_

LDO

VSSA

RX2C_P

VSSA

AUXDAC2

TEST/

ENABLE

CTRL_IN0

CTRL_IN1

VSSA

RX2C_N

VDDA1P3_

RX_RF

VDDA1P3_

RX_TX

VDDA1P3_

RX_LO

VDDA1P3_

RX_VCO_

LDO

VDDA1P3_

TX_LO_

BUFFER

CTRL_OUT0

CTRL_IN3

CTRL_IN2

P0_D9/

TX_D4_P

P0_D7/

TX_D3_P

P0_D5/

TX_D2_P

P0_D3/

TX_D1_P

P0_D1/

TX_D0_P

P0_D8/

TX_D4_N

P0_D6/

TX_D3_N

P0_D4/

TX_D2_N

P0_D10/

TX_D5_N

FB_CLK_P

FB_CLK_N

P0_D2/

TX_D1_N

VSSD

RX2B_P

CTRL_OUT1 CTRL_OUT2 CTRL_OUT3

P0_D0/

TX_D0_N

P0_D11/

TX_D5_P

RX2B_N

VSSA

CTRL_OUT6 CTRL_OUT5 CTRL_OUT4

VSSD

VDDD1P3_

DIG

RX_EXT_

LO_IN

RX_VCO_

LDO_OUT

VDDA1P1_

RX_VCO

CTRL_OUT7

EN_AGC

ENABLE

RX_

FRAME_P

RX_

FRAME_N

TX_

FRAME_P

DATA_

CLK_P

VSSD

RX1B_P

VSSA

TXNRX

SYNC_IN

VSSD

P1_D11/

RX_D5_P

TX_

FRAME_N

VSSD

DATA_

CLK_N

VDD_

INTERFACE

RX1B_N

VSSA

SPI_DI

SPI_CLK

CLK_OUT

P1_D10/

RX_D5_N

RX1C_P

VSSA

VDDA1P3_

TX_SYNTH

VDDA1P3_

RESETB

SPI_ENB

P1_D8/

RX_D4_N

P1_D9/

RX_D4_P

P1_D6/

RX_D3_N

P1_D7/

RX_D3_P

P1_D4/

RX_D2_N

P1_D5/

RX_D2_P

P1_D2/

RX_D1_N

P1_D3/

RX_D1_P

P1_D0/

RX_D0_N

P1_D1/

RX_D0_P

VSSD

RX1C_N

VSSA

RBIAS

AUXADC

SPI_DO

VSSA

RX1A_P

RX1A_N

TX1B_N

VSSA

TX_MON1

VSSA

TX1A_P

TX1A_N

TX1B_P

XTALP

XTALN

ANALOG I/O

DIGITAL I/O

NO CONNECT

DC POWER

GROUND

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