AD9361BBCZ datasheet(35/36 Pages) AD

35 / 36 page

Data Sheet

AD9361

Rev. D | Page 35 of 36

In FDD mode, the ENABLE and TXNRX pins can be remapped

to serve as real-time RX and TX data transfer control signals. In

this mode, the ENABLE pin enables or disables the receive signal

path, and the TXNRX pin enables or disables the transmit signal

path. In this mode, the ENSM is removed from the system for

control of all data flow by these pins.

SPI INTERFACE

The AD9361 uses a serial peripheral interface (SPI) to

communicate with the BBP. This interface can be configured

as a 4-wire interface with dedicated receive and transmit ports,

or it can be configured as a 3-wire interface with a bidirectional

data communication port. This bus allows the BBP to set all device

control parameters using a simple address data serial bus protocol.

Write commands follow a 24-bit format. The first six bits are

used to set the bus direction and number of bytes to transfer.

The next 10 bits set the address where data is to be written. The

final eight bits are the data to be transferred to the specified register

address (MSB to LSB). The AD9361 also supports an LSB-first

format that allows the commands to be written in LSB to MSB

format. In this mode, the register addresses are incremented for

multibyte writes.

Read commands follow a similar format with the exception that

the first 16 bits are transferred on the SPI_DI pin and the final

eight bits are read from the AD9361, either on the SPI_DO pin

in 4-wire mode or on the SPI_DI pin in 3-wire mode.

CONTROL PINS

Control Outputs (CTRL_OUT[7:0])

The AD9361 provides eight simultaneous real-time output signals

for use as interrupts to the BBP. These outputs can be configured to

output a number of internal settings and measurements that the

BBP can use when monitoring transceiver performance in different

situations. The control output pointer register selects what

information is output to these pins, and the control output enable

the BBP. Signals used for manual gain mode, calibration flags,

state machine states, and the ADC output are among the outputs

that can be monitored on these pins.

Control Inputs (CTRL_IN[3:0])

The AD9361 provides four edge detected control input pins. In

manual gain mode, the BBP can use these pins to change the gain

table index in real time. In transmit mode, the BBP can use two

of the pins to change the transmit gain in real time.

GPO PINS (GPO_3 TO GPO_0)

The AD9361 provides four, 3.3 V capable general-purpose logic

output pins: GPO_3, GPO_2, GPO_1, and GPO_0. These pins

can be used to control other peripheral devices such as regulators

and switches via the AD9361 SPI bus, or they can function as

slaves for the internal AD9361 state machine.

AUXILIARY CONVERTERS

AUXADC

The AD9361 contains an auxiliary ADC that can be used to

monitor system functions such as temperature or power output.

The converter is 12 bits wide and has an input range of 0 V to

1.25 V. When enabled, the ADC is free running. SPI reads provide

the last value latched at the ADC output. A multiplexer in front

of the ADC allows the user to select between the AUXADC input

pin and a built-in temperature sensor.

AUXDAC1 and AUXDAC2

The AD9361 contains two identical auxiliary DACs that can

provide power amplifier (PA) bias or other system functionality.

The auxiliary DACs are 10 bits wide, have an output voltage range

of 0.5 V to VDD_GPO − 0.3 V, a current drive of 10 mA, and

can be directly controlled by the internal enable state machine.

POWERING THE AD9361

The AD9361 must be powered by the following three supplies:

the analog supply (VDDD1P3_DIG/VDDAx = 1.3 V), the

interface supply (VDD_INTERFACE = 1.8 V), and the GPO

supply (VDD_GPO = 3.3 V).

For applications requiring optimal noise performance, it is

recommended that the 1.3 V analog supply be split and sourced

from low noise, low dropout (LDO) regulators. Figure 74 shows

the recommended method.

Figure 74. Low Noise Power Solution for the AD9361

For applications where board space is at a premium, and

optimal noise performance is not an absolute requirement, the

1.3 V analog rail can be provided directly from a switcher, and a

more integrated power management unit (PMU) approach can

be adopted. Figure 75 shows this approach.

Figure 75. Space-Optimized Power Solution for the AD9361

3.3V

1.8V

1.3V_A

1.3V_B

ADP2164

ADP1755

LDO

ADP5040

1.2A

BUCK

300mA

LDO

300mA

LDO

AD9361

1.3V

VDDD1P3_DIG/VDDAx

1.8V

VDD_INTERFACE

3.3V

VDD_GPO

AD9361BBCZ датащи(PDF) 35 Page - Analog Devices

AD9361BBCZ датащи(HTML) 35 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

датащи скачать

ссылки URL