AD9361BBCZ datasheet(6/36 Pages) AD

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AD9361

Data Sheet

Rev. D | Page 6 of 36

Parameter1

Symbol

Min

Typ

Max

Unit

Test Conditions/

Comments

Logic Outputs

Output Voltage

High

1375

Low

1025

Output Differential Voltage

150

Programmable in 75 mV

steps

Output Offset Voltage

1200

GENERAL-PURPOSE OUTPUTS

Output Voltage

High

VDD_GPO × 0.8

Low

VDD_GPO × 0.2

Output Current

SPI TIMING

VDD_INTERFACE = 1.8 V

SPI_CLK

Period

tCP

Pulse Width

tMP

SPI_ENB Setup to First SPI_CLK

Rising Edge

tSC

Last SPI_CLK Falling Edge to

SPI_ENB Hold

tHC

SPI_DI

Data Input Setup to SPI_CLK

Data Input Hold to SPI_CLK

SPI_CLK Rising Edge to Output

Data Delay

4-Wire Mode

tCO

3-Wire Mode

tCO

Bus Turnaround Time, Read

tHZM

tCO (max)

After BBP drives the last

address bit

Bus Turnaround Time, Read

tHZS

tCO (max)

After AD9361 drives the

last data bit

DIGITAL DATA TIMING (CMOS),

VDD_INTERFACE = 1.8 V

DATA_CLK Clock Period

tCP

16.276

61.44 MHz

DATA_CLK and FB_CLK Pulse

Width

tMP

45% of tCP

55% of tCP

TX Data

TX_FRAME, P0_D, and

P1_D

Setup to FB_CLK

tSTX

Hold to FB_CLK

tHTX

DATA_CLK to Data Bus Output

Delay

tDDRX

1.5

DATA_CLK to RX_FRAME Delay

tDDDV

1.0

Pulse Width

ENABLE

tENPW

tCP

TXNRX

tTXNRXPW

tCP

FDD independent ENSM

mode

TXNRX Setup to ENABLE

tTXNRXSU

TDD ENSM mode

Bus Turnaround Time

Before RX

tRPRE

2 × tCP

TDD mode

After RX

tRPST

2 × tCP

TDD mode

Capacitive Load

Capacitive Input

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