AD9361BBCZ datasheet(5/36 Pages) AD

5 / 36 page

Data Sheet

AD9361

Rev. D | Page 5 of 36

Parameter1

Symbol

Min

Typ

Max

Unit

Test Conditions/

Comments

TX MONITOR INPUTS (TX_MON1,

TX_MON2)

Maximum Input Level

dBm

Dynamic Range

Accuracy

LO SYNTHESIZER

LO Frequency Step

2.4

2.4 GHz, 40 MHz

reference clock

Integrated Phase Noise

800 MHz

0.13

° rms

100 Hz to 100 MHz,

30.72 MHz reference clock

(doubled internally for RF

synthesizer)

2.4 GHz

0.37

° rms

100 Hz to 100 MHz,

40 MHz reference clock

5.5 GHz

0.59

° rms

100 Hz to 100 MHz,

40 MHz reference clock

(doubled internally for RF

synthesizer)

REFERENCE CLOCK (REF_CLK)

REF_CLK is either the input

to the XTALP/XTALN pins

or a line directly to the

XTALN pin

Input

Frequency Range

MHz

Crystal input

MHz

External oscillator

Signal Level

1.3

V p-p

AC-coupled external

oscillator

AUXILIARY CONVERTERS

ADC

Resolution

Bits

Input Voltage

Minimum

0.05

Maximum

VDDA1P3_BB − 0.05

DAC

Resolution

Bits

Output Voltage

Minimum

0.5

Maximum

VDD_GPO − 0.3

Output Current

DIGITAL SPECIFICATIONS (CMOS)

Logic Inputs

Input Voltage

High

VDD_INTERFACE × 0.8

VDD_INTERFACE

Low

VDD_INTERFACE × 0.2

Input Current

High

−10

+10

μA

Low

−10

+10

μA

Logic Outputs

Output Voltage

High

VDD_INTERFACE × 0.8

Low

VDD_INTERFACE × 0.2

DIGITAL SPECIFICATIONS (LVDS)

Logic Inputs

Input Voltage Range

825

1575

Each differential input in

the pair

Input Differential Voltage

Threshold

−100

+100

Receiver Differential Input

Impedance

100

Ω

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