MCP6S92 datasheet(20/40 Pages) MICROCHIP

20 / 40 page

 2004 Microchip Technology Inc.

DS21908A-page 20

MCP6S91/2/3

4.4

Rail-to-Rail VREF Input

The VREF input is intended to be driven by a low-

impedance voltage source. The source driving the

VREF pin should have an output impedance less than

0.1

Ω to maintain reasonable gain accuracy. The supply

voltage VSS and VDD usually meet this requirement.

RLAD presents a load at the VREF pin to the external

circuit (ZIN_REF ≈ (5 kΩ/G)||(6 pF)), which depends on

the gain. Any source driving the VREF pin must be

capable of driving a load as heavy as 0.16 k

Ω||6 pF

(G = 32).

The absolute maximum voltages that can be applied to

the reference input pin (VREF) are VSS –0.3V and

VDD + 0.3V. Voltages on the inputs that exceed this

absolute maximum rating can cause excessive current

to flow into or out of this pin. Current beyond ±2 mA can

cause possible reliability problems. Because an

external series resistor cannot be used (for low gain

error), the external circuit must ensure that VREF is

between VSS – 0.3V and VDD +0.3V.

The VIVR_REF spec shows the region of normal

operation for the VREF pin (VSS to VDD). Staying within

this region ensures proper operation of the PGA and its

surrounding circuitry.

4.5

Shutdown Mode

These PGAs use a software shutdown command.

When the SPI interface sends a shutdown command,

the internal op amp is shut down and its output placed

in a High-Z state.

The resistive ladder is always connected between

VREF and VOUT; even in shutdown. This means that the

output resistance will be on the order of 5 k

Ω, with a

path for output signals to appear at the input.

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