MCP6S92 datasheet(28/40 Pages) MICROCHIP

28 / 40 page

 2004 Microchip Technology Inc.

DS21908A-page 28

MCP6S91/2/3

6.3.2

SUPPLY BYPASS

Use a local bypass capacitor (0.01 µF to 0.1 µF) within

2mm of the VDD pin. It must connect directly to the

ground plane. A multi-layer ceramic chip capacitor, or

high-frequency equivalent, works best.

Use a bulk bypass capacitor (2.2 µF to 10 µF) within

100 mm of the VDD pin. It needs to connect to the

ground plane. A multi-layer ceramic chip capacitor,

tantalum or high-frequency equivalent, works best.

This capacitor may be shared with other nearby analog

parts.

6.3.3

INPUT SOURCE IMPEDANCE

The sources driving the inputs of the PGAs need to

have reasonably low source impedance at higher

frequencies. Figure 6-4 shows how the external source

impedance (RS), PGA package pin capacitance (CP1)

and PGA package pin-to-pin capacitance (CP2) form a

positive feedback voltage divider network. Feedback to

the selected channel may cause frequency response

peaking and step response overshoot and ringing.

Feedback to an unselected channel will produce

crosstalk.

FIGURE 6-4:

Positive Feedback Path.

Figure 2-6 shows the crosstalk (referred to input) that

results when a hostile signal is connected to CH1, input

CH0 is selected and RS is connected from CH0 to

GND. A gain of +32 was chosen for this plot because it

demonstrates the worst-case behavior. Increasing RS

increases the crosstalk as expected. At a source

impedance of 10 k

Ω, there is noticeable peaking in the

response; this is due to positive feedback.

Most designs should use a source resistance (RS) no

larger than 10 k

Ω. Careful attention to layout parasitics

and proper component selection will help minimize this

effect. When a source impedance larger than 10 k

Ω

must be used, place a capacitor in parallel to CP1 to

reduce the positive feedback. This capacitor needs to

be large enough to overcome gain (or crosstalk) peak-

ing, yet small enough to allow a reasonable signal

bandwidth.

6.3.4

SIGNAL COUPLING

The input pins of the MCP6S91/2/3 family of PGAs are

high-impedance. This makes them especially suscepti-

ble to capacitively-coupled noise. Using a ground plane

helps reduce this problem.

When noise is capacitively coupled, the ground plane

provides additional shunt capacitance to ground. When

noise is magnetically coupled, the ground plane

reduces the mutual inductance between traces.

Increasing the separation between traces makes a

significant difference.

Changing the direction of one of the traces can also

reduce magnetic coupling. It may help to locate guard

traces next to the victim trace. They should be on both

sides of, and as close as possible to, the victim trace.

Connect the guard traces to the ground plane at both

ends. Also connect long guard traces to the ground

plane in the middle.

6.3.5

HIGH-FREQUENCY ISSUES

Because the MCP6S91/2/3 PGAs’ frequency response

reaches unity gain at 64 MHz when G = 16 and 32, it is

important to use good PCB layout techniques. Any

parasitic-coupling at high-frequency

might cause

undesired peaking. Filtering high-frequency signals

(i.e., fast edge rates) can help. To minimize high-

frequency problems:

• Use complete ground and power planes

• Use HF, surface-mount components

• Provide clean supply voltages and bypassing

• Keep traces short and straight

• Try a linear power supply (e.g., a LDO)

VIN

MCP6S9X

VOUT

CP1

CP2

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