MCP6S92 datasheet(18/40 Pages) MICROCHIP

18 / 40 page

 2004 Microchip Technology Inc.

DS21908A-page 18

MCP6S91/2/3

4.0

ANALOG FUNCTIONS

The MCP6S91/2/3 family of Programmable Gain

Amplifiers (PGA) is based on simple analog building

blocks (see Figure 4-1). Each of these blocks will be

explained in more detail in the following subsections.

FIGURE 4-1:

PGA Block Diagram.

4.1

Input MUX

The MCP6S91 has one input, while the MCP6S92 and

MCP6S93 have two inputs (see Figure 4-1).

For the lowest input current, float unused inputs. Tying

these pins to a voltage near the active channel’s bias

voltage also works well. For simplicity, they can be tied

to VSS or VDD, but the input current may increase.

The one-channel MCP6S91 has approximately the

same input bias current as the two-channel MCP6S92

and MCP6S93.

The input offset voltage mismatch between channels

(

∆V

OS) is, ideally, 0 µV. The input MUX uses CMOS

transmission gates that have drain-source (channel)

resistance, but no offset voltage. The histogram in

Figure 2-8 reflects the measurement repeatability

(i.e., noise power bandwidth) rather than the actual

mismatch. Reducing the measurement bandwidth will

produce a more narrow histogram and give an aver-

age closer to 0 µV.

4.2

Internal Op Amp

The internal op amp gives the right combination of

bandwidth, accuracy and flexibility.

4.2.1

COMPENSATION CAPACITORS

The internal op amp has three compensation capaci-

tors (comp. caps.) connected to a switching network.

They are selected to give good small-signal bandwidth

at high gains and good slew rates (full-power band-

width) at low gains. The change in bandwidth as gain

changes is between 2 and 12 MHz. Refer to Table 4-1

for more information.

TABLE 4-1:

GAIN VS. INTERNAL

COMPENSATION

CAPACITOR

4.2.2

RAIL-TO-RAIL CHANNEL INPUTS

The input stage of the internal op amp uses two differ-

ential input stages in parallel; one operates at low VIN

(input voltage), while the other operates at high VIN.

With this topology, the internal inputs can operate to

0.3V past either supply rail. The input offset voltage is

measured at both VIN =VSS – 0.3V and VDD + 0.3V to

ensure proper operation.

The transition between the two input stages occurs

when VIN ≈ VDD – 1.5V. For the best distortion and gain

linearity, avoid this region of operation.

MCP6S91 – One input (CH0), no SO pin

MCP6S92 – Two inputs (CH0, CH1), VREF tied

internally to VSS, no SO pin

MCP6S93 – Two inputs (CH0, CH1)

VOUT

VREF

VDD

SCK

CH1

CH0

VSS

MUX

SPI™

Logic

Gain

Switches

Gain

(V/V)

Internal

Comp.

Cap.

GBWP

(MHz)

Typ.

(V/µs)

Typ.

FPBW

(MHz)

Typ.

(MHz)

Typ.

Large

4.0

0.30

Large

4.0

0.30

4Medium

0.70

5Medium

0.70

Medium

0.70

2.4

Medium

0.70

2.0

Small

1.6

Small

1.6

2.0

Note 1:

FPBW is the Full-Power Bandwidth.

These numbers are based on VDD =5.0V.

No changes in DC performance

(e.g., VOS) accompany a change in

compensation capacitor.

BW is the closed-loop, small signal -3 dB

bandwidth.

MCP6S92 датащи(PDF) 18 Page - Microchip Technology

MCP6S92 датащи(HTML) 18 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

датащи скачать

ссылки URL