AM3703CUS datasheet(237/280 Pages) TI

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AM3715, AM3703

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SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

The I2C controller supports the multi-master mode which allows more than one device capable of

controlling the bus to be connected to it. Each I2C device is recognized by a unique address and can

operates as either transmitter or receiver, according to the function of the device. In addition to being a

transmitter or receiver, a device connected to the I2C bus can also be considered as master or slave when

performing data transfers. This data transfer is carried out via two serial bidirectional wires:

•

An SDA data line

•

An SCL clock line

In Figure 6-53 the data transfer is in master or slave configuration with 7-bit addressing format.

The I2C interface is compliant with Philips I2C specification version 2.1. It supports standard mode (up to

100K bits/s), fast mode (up to 400K bits/s) and high-speed mode (up to 3.4Mb/s).

6.6.5.1

I2C

—Standard and Fast Modes

Table 6-97. I2C

—Standard and Fast Modes

NO.

PARAMETER

STANDARD MODE

FAST MODE

UNIT

MIN

MAX

MIN

MAX

fscl

Frequency, clock i2cx_scl(4)

100

400

kHz

tw(sclH)

Pulse duration, clock i2cx_scl(4) high

4.0

0.6

μs

tw(sclL)

Pulse duration, clock i2cx_scl(4) low

4.7

1.3

μs

tsu(sdaV-sclH)

Setup time, data i2cx_sda(4) valid before clock

250

100(1)

i2cx_scl(4) active level

th(sclH-sdaV)

Hold time, data i2cx_sda(4) valid after clock

0(2)

3.45(3)

0(2)

0.9(3)

μs

i2cx_scl(4) active level

tsu(sdaL-sclH)

Setup time, clock i2cx_scl(4) high after data

4.7

0.6

μs

i2cx_sda(4) low (for a START(5) condition or a

repeated START condition)

th(sclH-sdaH)

Hold time, data i2cx_sda low level after clock

4.0

0.6

μs

i2cx_scl(4) high level (STOP condition)

th(sclH-RSTART)

Hold time, data i2cx_sda(4) low level after

4.0

0.6

μs

clock i2cx_scl(4) high level (for a repeated

START condition)

tw(sdaH)

Pulse duration, data i2cx_sda(4) high between

4.7(4)

1.3

μs

STOP and START conditions

tR(scl)

Rise time, clock i2cx_scl(4)

1000

20 +

300

0.1CB

tF(scl)

Fall time, clock i2cx_scl(4)

300

20 +

300

0.1CB

tR(sda)

Rise time, data i2cx_sda(4)

1000

20 +

300

0.1CB

tF(sda)

Fall time, data i2cx_sda(4)

300

20 +

300

0.1CB

Capacitive load for each bus line

400

(1) A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tsu(SDAV-SCLH) ≥ 250 ns must then be

met. This is automatically the case if the device does not stretch the low period of the i2cx_scl(4). If such a device does stretch the low

period of the i2cx_scl(4), it must output the next data bit to the i2cx_sda(4) line tr(SDA) max + tsu(SDAV-SCLH) = 1000 + 250 = 1250 ns

(according to the standard-mode I2C-bus specification) before the i2cx_scl(4) line is released.

(2) The device provides (via the I2C bus) a minimum hold time (= I2C_FCLK period x (PSC+1) x 4) for the i2cx_sda(4) signal (see the fall

and rise times of i2cx_scl(4)) to bridge the undefined region of the falling edge of i2cx_scl(4).

(3) The maximum th(SCLH-SDA) has only to be met if the device does not stretch the low period of the i2cx_scl

(4) signal.

(4) In i2cx, x is equal to 1, 2, 3, or 4. Note that I2C4 is master transmitter only.

(5) After this time, the first clock is generated.

Timing Requirements and Switching Characteristics

237

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