AM3703CUS datasheet(234/280 Pages) TI

234 / 280 page

AM3715, AM3703

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

www.ti.com

6.6.4

Multiport High-Speed Universal Serial Bus (HS-USB)

NOTE

For more information, see High-Speed USB Host Subsystem and High-Speed USB OTG

Controller / High-Speed USB OTG Controller and High-Speed USB Host Subsystem and

High-Speed USB OTG Controller / High-Speed USB Host Subsystem sections of the

AM/DM37x Multimedia Device Technical Reference Manual (literature number SPRUGN4).

In addition to the full-speed (FS) USB controller, a high-speed (HS) USB OTG controller is incorporated in

the device. It allows high-speed transactions (up to 480 Mbit/s) on the USB ports 0, 1, 2, and 3 described

below:

•

Port 0:

– 12-bit slave mode (SDR)

•

Ports 1 and 2:

– 12-bit master mode (SDR)

•

Port 3:

6.6.4.1

HSUSB0

—Port 0—12-bit Slave Mode

Table 6-92 and Table 6-93 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 6-51).

Table 6-91. HSUSB0 Timing Conditions

—12-bit Slave Mode

TIMING CONDITION PARAMETER

VALUE

UNIT

Input Conditions

Input signal rise time

Input signal fall time

Output Condition

CLOAD

Output load capacitance(1)

3.5

(1) Buffer strength configuration: LB0 = 0.

Table 6-92. HSUSB0 Timing Requirements

—12-bit Slave Mode(3) (4)

NO.

PARAMETER

OPP100

UNIT

MIN

MAX

HSU0

fp(CLK)

hsusb0_clk clock frequency(1)

60.03

MHz

tJ(CLK)

Cycle jitter(2), hsusb0_clk

500

HSU3

ts(DIRV-CLKH)

Setup time, hsusb0_dir valid before hsusb0_clk rising edge

6.68

ts(NXTV-CLKH)

Setup time, hsusb0_nxt valid before hsusb0_clk rising edge

6.68

HSU4

th(CLKH-DIRIV)

Hold time, hsusb0_dir valid after hsusb0_clk rising edge

th(CLKH-NXT/IV)

Hold time, hsusb0_nxt valid after hsusb0_clk rising edge

HSU5

ts(DATAV-CLKH)

Setup time, hsusb0_data[0:7] valid before hsusb0_clk rising edge

6.68

HSU6

th(CLKH-DATIV)

Hold time, hsusb0_data[0:7] valid after hsusb0_clk rising edge

(1) Related with the input maximum frequency supported by the USB module.

(2) Maximum cycle jitter supported by hsusb0_clk input clock

(3) The timing requirements are assured up to the cycle jitter error condition specified.

(4) See Section 4.3.4, Processor Clocks.

234

Timing Requirements and Switching Characteristics

Submit Documentation Feedback

Product Folder Link(s): AM3715 AM3703

AM3703CUS датащи(PDF) 234 Page - Texas Instruments

AM3703CUS датащи(HTML) 234 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL