AM3703CUS datasheet(239/280 Pages) TI

239 / 280 page

AM3715, AM3703

www.ti.com

SPRS616F

– JUNE 2010 – REVISED AUGUST 2011

Table 6-99. I2C Correspondence Standard vs Data Manual Timing References

STANDARD-I2C

Standard/Fast Modes

High-Speed Mode

fscl

FSCL

FSCLH

tw(sclH)

THIGH

tw(sclL)

TLOW

tsu(sdaV-sclH)

TSU;DAT

th(sclH-sdaV)

TSU;DAT

tsu(sdaL-sclH)

TSU;STA

th(sclH-sdaH)

THD;STA

th(sclH-RSTART)

TSU;STO

tw(sdaH)

TBUF

6.6.6

HDQ / 1-Wire Interface (HDQ/1-Wire)

NOTE

For more information, see HDQ/1-Wire / HDQ/1-Wire chapter of the AM/DM37x Multimedia

Device Technical Reference Manual (literature number SPRUGN4).

The module is intended to work with both HDQ and 1-Wire protocols. The protocols use a single wire to

communicate between the master and the slave. The protocols employ an asynchronous return to one

mechanism where, after any command, the line is pulled high.

6.6.6.1

HDQ/1-Wire

—HDQ Mode

Table 6-100 and Table 6-102 assume testing over the recommended operating conditions and electrical

characteristic conditions below (see Figure 6-55 through Figure 6-59).

Table 6-100. HDQ Interface Read Timing

PARAMETER

DESCRIPTION

MIN

TYP

MAX

UNIT

tCYCH

Read bit window timing

190

250

μs

tHW1

Read one data valid after HDQ low

32(2)

66(2)

μs

tHW0

Read zero data hold after HDQ low

70(2)

145(2)

μs

tRSPS

Response time from HDQ slave device(1)

190

320

μs

(1) Defined by software

(2) If the HDQ slave device drives a logic-low state after tHW0 max, it can be interpreted as a break pulse. For more information see

Table 6-101 and the HDQ/1-Wire chapter of the AM/DM37x Multimedia Device Technical Reference Manual (literature number

SPRUGN4).

Table 6-101. HDQ Sampling Cases(1)

CASES

FIRST SAMPLING (at 68

µs)

SECOND SAMPLING (at 180

µs)

L (logic-low state)

H (logic-high state)

L (logic-low state)

H (logic-high state)

(1) The different cases can be interpreted as follows:

–

Case 1: If a logic-low state is present at the first sampling time and also at the second sampling time, the receive data can be

interpreted as a break pulse.

–

Case 2: If a logic-low state is present at the first sampling time and a logic-high state is present at the second sampling time, the

receive data on the line is a zero (data).

–

Case 3: Undefined.

–

Case 4: If a logic-high state is present at the first sampling time and also at the second sampling time, the receive data on the line is

a one (data).

Timing Requirements and Switching Characteristics

239

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