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STM8L052C6 датащи(PDF) 80 Page - STMicroelectronics |
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STM8L052C6 датащи(HTML) 80 Page - STMicroelectronics |
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80 / 102 page ![]() Electrical parameters STM8L052C6 80/102 Doc ID 023331 Rev 1 Figure 27. Typical NRST pull-up current Ipu vs VDD The reset network shown in Figure 28 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max. level specified in Table 39. Otherwise the reset is not taken into account internally. For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If the NRST signal is used to reset the external circuitry, attention must be paid to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. The minimum recommended capacity is 10 nF. Figure 28. Recommended NRST pin configuration ai18225V2 0 20 40 60 80 100 120 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] -40°C 25°C 85°C EXTERNAL RESET CIRCUIT STM8 Filter RPU VDD INTERNAL RESET NRST 0.1 µF (Optional) |
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