STM8L052C6 datasheet(65/102 Pages) STMICROELECTRONICS

65 / 102 page

STM8L052C6

Electrical parameters

Doc ID 023331 Rev 1

65/102

In the following table, data is based on characterization results, unless otherwise specified.

RTC enabled, LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.

LCD enabled with internal LCD booster VLCD = 3 V , 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD

connected.

Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for extenal crystal, the LSE consumption

(IDD LSE) must be added. Refer to Table 29.

RTC enabled. Clock source = LSE.

Wakeup time until start of interrupt vector fetch.

The first word of interrupt routine is fetched 4 CPU cycles after tWU.

ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.

Table 22.

Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal

Symbol

Parameter

Condition(1)

Typ

Unit

IDD(AH)

(2)

Supply current in Active-halt

mode

VDD = 1.8 V

LSE

1.15

µA

LSE/32(3)

1.05

VDD = 3 V

LSE

1.30

LSE/32(3)

1.20

VDD = 3.6 V

LSE

1.45

LSE/32(3)

1.35

No floating I/O, unless otherwise specified.

Based on measurements on bench with 32.768 kHz external crystal oscillator.

RTC clock is LSE divided by 32.

Table 23.

Total current consumption and timing in Halt mode at VDD = 1.8 to 3.6 V

Symbol

Parameter

Condition(1)

Typ

Max

Unit

IDD(Halt)

Supply current in Halt mode

(Ultra-low-power ULP bit =1 in

the PWR_CSR2 register)

TA = -40 °C to 25 °C

350

1400(2)

TA = 55 °C

580

2000

TA = 85 °C

1160

2800(2)

IDD(WUHalt)

Supply current during wakeup

time from Halt mode (using

HSI)

2.4

tWU_HSI(Halt)

(3)(4)

Wakeup time from Halt to Run

mode (using HSI)

4.7

µs

tWU_LSI(Halt)

(3)(4)

Wakeup time from Halt mode

to Run mode (using LSI)

150

µs

TA = -40 to 85 °C, no floating I/O, unless otherwise specified.

Tested in production.

ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.

Wakeup time until start of interrupt vector fetch.

The first word of interrupt routine is fetched 4 CPU cycles after tWU.

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