AD9920ABBCZ datasheet(22/112 Pages) AD

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AD9920A

Rev. B | Page 22 of 112

DIGITAL DATA OUTPUTS

The AD9920A data output and DCLK phase are programmable

using the DOUTPHASE registers (Address 0x39, Bits[13:0]).

DOUTPHASEP (Bits[5:0]) selects any edge location from 0 to

63, as shown in Figure 25. DOUTPHASEN (Bits[13:8]) does

not actually program the phase of the data outputs but is used

internally and should always be programmed to a value of

DOUTPHASEP plus 32 edges. For example, if DOUTPHASEP

is set to 0, DOUTPHASEN should be set to 32 (0x20).

Normally, the data output and DCLK signals track in phase,

based on the contents of the DOUTPHASE registers. The DCLK

output phase can also be held fixed with respect to the data out-

puts by setting the DCLKMODE register high (Address 0x39,

Bit 16). In this mode, the DCLK output remains at a fixed phase

equal to a delayed version of CLI, and the data output phase

remains programmable.

The pipeline delay through the AD9920A is shown in Figure 26.

After the CCD input is sampled by SHD, there is a 16-cycle

delay until the data is available.

P[0]

P[64] = P[0]

PIXEL

PERIOD

P[16]

P[32]

P[48]

DOUT

DCLK

tOD

NOTES

1. DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD.

2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 64 DIFFERENT LOCATIONS.

3. DCLK CAN BE INVERTED WITH RESPECT TO DOUT BY USING THE DCLKINV REGISTER.

Figure 25. Digital Output Phase Adjustment Using DOUTPHASEP Register

NOTES

1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0.

2. HIGHER VALUES OF SHD AND/OR DOUTPHASE SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.

3. RECOMMENDED VALUE FOR DOUTPHASE IS TO USE SHPLOC OR UP TO 15 EDGES FOLLOWING SHPLOC.

DCLK

DOUT

CCDIN

CLI

SHD

(INTERNAL)

ADC DOUT

(INTERNAL)

NN + 2

N + 1

N + 3

N + 13

N + 12

N + 11

N + 10

N + 9

N + 8

N + 7

N + 6

N + 5

N + 4

N + 14

SAMPLE PIXEL N

N + 16

N + 17

N + 15

N – 14

N – 4

N – 5

N – 6

N – 7

N – 8

N – 9

N – 10

N – 11

N – 12

N – 13

N – 3

N – 2

N – 1

N + 1

N – 15

N – 16

N – 17

tCLIDLY

PIPELINE LATENCY = 16 CYCLES

N – 14

N – 4

N – 5

N – 6

N – 7

N – 8

N – 9

N – 10

N – 11

N – 12

N – 13

N – 3

N – 2

N – 1

N + 1

N – 15

N – 16

N – 17

tDOUTINH

Figure 26. Digital Data Output Pipeline Delay

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