AD9920ABBCZ datasheet(100/112 Pages) AD

100 / 112 page

AD9920A

Rev. B | Page 100 of 112

Address

Data Bits

Default

Value

Update

Type

Name

Description

0x36

[2:0]

0x01

SCK

H1DRV

H1 drive strength.

0 = off.

1 = 4.3 mA.

2 = 8.6 mA.

3 = 12.9 mA.

4 = 17.3 mA.

5 = 21.6 mA.

6 = 25.9 mA.

7 = 30.2 mA.

[6:4]

0x1

H2DRV

H2 drive strength (same range as H1DRV).

[10:8]

0x1

H3DRV

H3 drive strength (same range as H1DRV).

[14:12]

0x1

H4DRV

H4 drive strength (same range as H1DRV).

[18:16]

0x1

HLDRV

HL drive strength.

0 = off.

1 = 4.3 mA.

2 = 8.6 mA.

3 = 12.9 mA.

4 = 4.3 mA.

5 = 8.6 mA.

6 = 12.9 mA.

7 = 17.3 mA.

[22:20]

0x1

RGDRV

RG drive strength (same range as HLDRV).

0x37

[2:0]

0x1

SCK

H5DRV

H5 drive strength (same range as H1DRV).

[6:4]

0x1

H6DRV

H6 drive strength (same range as H1DRV).

[10:8]

0x1

H7DRV

H7 drive strength (same range as H1DRV).

[14:12]

0x1

H8DRV

H8 drive strength (same range as H1DRV).

[18:16]

0x1

Test

Test use only. Set to 1.

[22:20]

0x1

Test

Test use only. Set to 1.

0x38

[5:0]

SCK

SHDLOC

SHD sampling edge location.

[13:8]

0x20

SHPLOC

SHP sampling edge location.

[21:16]

0x10

SHPWIDTH

SHP width (controls input dc restore switch active time).

0x39

[5:0]

SCK

DOUTPHASEP

DOUT phase control, positive edge. Specifies location of DOUT.

[13:8]

0x20

DOUTPHASEN

DOUT phase control, negative edge. Always set to DOUTPHASEP +

32 edges to maintain 50% duty cycle of internal DOUTPHASE clocking.

[16]

DCLKMODE

DCLK mode.

0 = DCLK tracks DOUT.

1 = DCLK phase is fixed.

[18:17]

Test

Test use only. Set to 0.

[19]

DCLKINV

Invert DCLK output.

0 = no inversion.

1 = inversion of DCLK.

[22:20]

Test

Test use only. Set to 0.

0x3A

[27]

SCK

Test

Do not access, or set to 0.

0x3B

[27]

SCK

UNUSED

Do not access, or set to 0.

0x3C

[27]

SCK

Test

Do not access, or set to 0.

0x3D

[27]

SCK

UNUSED

Do not access, or set to 0.

0x3E

[27]

SCK

Test

Do not access, or set to 0.

0x3F

[27]

SCK

UNUSED

Do not access, or set to 0.

Table 58. Test Registers—Do Not Access

Address

Data Bits

Default Value

Update Type

Name

Description

0x40 to 0x6F

Test registers. Do not access.

AD9920ABBCZ датащи(PDF) 100 Page - Analog Devices

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