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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9920ABBCZ датащи(PDF) 99 Page - Analog Devices |
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AD9920ABBCZ датащи(HTML) 99 Page - Analog Devices |
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99 / 112 page  AD9920A Rev. B | Page 99 of 112 Address Data Bits Default Value Update Type Name Description 0x2C [4:0] 0 SCK FIELD6 Selected sixth field in the mode register. [9:5] 0 FIELD7 Selected seventh field in the mode register. 0x2D [27] 0 SCK UNUSED Do not access, or set to 0. 0x2E [27] 0 SCK UNUSED Do not access, or set to 0. 0x2F [27] 0 SCK UNUSED Do not access, or set to 0. Table 57. Timing Core Registers Address Data Bits Default Value Update Type Name Description 0x30 [5:0] 0 SCK H1POSLOC H1 rising edge location in HCLK Mode 1, Mode 2, and Mode 3. Phase 3 (H7/H8) rising edge location in 3-phase mode. [13:8] 0x20 H1NEGLOC H1 falling edge location in HCLK Mode 1, Mode 2, and Mode 3. Phase 3 (H7/H8) falling edge location in 3-phase mode. [16] 0x01 Test Test use only. Set to 1. 0x31 [5:0] 0 SCK H2POSLOC H2 rising edge location in HCLK Mode 2. H5 rising edge location in HCLK Mode 3. Phase 2 (H5/H6) rising edge location in 3-phase mode. [13:8] 0x20 H2NEGLOC H2 falling edge location in HCLK Mode 2. H5 falling edge location in HCLK Mode 3. Phase 2 (H5/H6) falling edge location in 3-phase mode. [16] 0x01 Test Test use only. Set to 1. 0x32 [5:0] 0 SCK HLPOSLOC HL rising edge location. [13:8] 0x20 HLNEGLOC HL falling edge location. [16] 0x01 Test Test use only. Set to 1. 0x33 [5:0] 0 SCK H3P1POSLOC Phase 1 (H1/H2) rising edge location in 3-phase mode. [13:8] 0x20 H3P1NEGLOC Phase 1 (H1/H2) falling edge location in 3-phase mode. [16] 0x01 Test Test use only. Set to 1. 0x34 [5:0] 0 SCK RGPOSLOC RG rising edge location. [13:8] 0x10 RGNEGLOC RG falling edge location. [16] 0x01 Test Test use only. Set to 1. 0x35 [0] 0 SCK H1HBLKRETIME Retime H1 HBLK to internal clock. Enabling retime adds one half cycle delay to HBLK position. 0 = no retime. 1 = retime. [1] 0 H2HBLKRETIME Retime H2 HBLK to internal clock. [2] 0 HLHBLKRETIME Retime HL HBLK to internal clock. [3] 0 H3PHBLKRETIME Retime H3 HBLK to internal clock. [7:4] 0 HCLK_WIDTH Enables wide H-clocks during HBLK interval. Set to 0 to disable. [8] 0 Test Test use only. Set to 0. [9] 0 HLHBLK 1 = enable HBLK for HL. [19:10] 0 Test Test use only. Set to 0. [20] 0 H1FINERETIME Adds one additional retime operation to H1 HBLK signal. [21] 0 H2FINERETIME Adds one additional retime operation to H2 HBLK signal. [22] 0 HLFINERETIME Adds one additional retime operation to HL HBLK signal. [23] 0 H3PFINERETIME Adds one additional retime operation to H3P HBLK signal (3-phase mode). |
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