AD9920ABBCZ datasheet(97/112 Pages) AD

97 / 112 page

AD9920A

Rev. B | Page 97 of 112

Table 53. Miscellaneous Registers

Address

Data

Bits

Default

Value

Default

Update

Type

Name

Description

0x10

[0]

SCK

SW_RST

Software reset. Bit self-clears to 0 when a reset occurs.

1 = reset Address 0x00 to Address 0xFF back to default values.

0x11

[0]

OUT_CONTROL

0 = make all outputs dc inactive.

1 = enable outputs at next VD edge.

0x12

[0]

0x01

SCK

RST_SYNC_EN

0 = configure SYNC/RST as SYNC pin.

1 = configure SYNC/RST as RST pin (default configuration is RST).

[4:1]

Test

Test mode only. Must be set to 0.

0x13

[0]

0x01

SCK

SYNCENABLE

1 = external synchronization enable. Configure SYNC/RST pin as an input.

[1]

SYNCPOL

SYNC active polarity.

[2]

SYNCSUSPEND

Suspend clocks during SYNC active pulse.

0 = don’t suspend.

1 = suspend.

[3]

ENH_SYNC_EN

1 = enable enhanced sync/shutter operations.

[4]

SYNC_MASK_HD

1 = mask HD during SYNCSUSPEND.

[5]

0x01

SYNC_MASK_VD

1 = mask VD during SYNCSUSPEND.

[6]

0x01

SYNC_MASK_V

1 = mask XV outputs during SYNCSUSPEND.

[7]

Test

Test mode only. Must be set to 0.

[12:8]

Test

Test mode only. Must be set to 0.

[13]

Test

Test mode only. Must be set to 0.

[14]

SYNC_EDGE_EN

1 = enable SYNC to use only one edge to reset.

[15]

SYNC_RST_SHUTEN

1 = enable reset of the shutter control after SYNC operation occurs.

[16]

GPO_RST_SYNC

1 = reset shutter and GPO control at SYNC operation.

[17]

SYNC_CNT_INC

1 = increment field counter by 1 when SYNC occurs.

0 = reset to 0.

[19:18]

UNUSED

Set unused bits to 0.

[23:20]

Test

Test mode only. Must be set to 0.

[24]

SWSYNC

1 = initiate software SYNC event (self-clears to 0 after SYNC).

[25]

REG_RST_SHUT

1 = force shutter control to reset until REG_RST_SHUT = 0.

0x14

[0]

SCK

TGCORE_RST

Timing core reset bar.

0 = reset TG core.

1 = resume operation.

0x15

[0]

SCK

OSC_RST

CLO oscillator reset bar.

0 = oscillator in power-down state.

1 = resume oscillator operation.

0x16

[27:0]

0x01

SCK

Test

Test mode only. Must be set to 1.

0x17

[12:0]

SCK

Update

Serial update line. Sets the line (HD) within the field to update the

VD-updated registers.

[13]

PREVENTUP

Prevents the update of the VD-updated registers.

0 = normal update.

1 = prevent update of VD-updated registers.

0x18

[27:0]

SCK

Test

Test mode only. Set to 0.

0x19

[27:0]

SCK

Test

Test mode only. Set to 0.

0x1A

[27:0]

SCK

Test

Test mode only. Set to 0.

0x1B

[27:0]

0x0A

SCK

Test

Test mode only. Set to 0x0A.

0x1C

[23:0]

SCK

VSGSELECT

1 = each bit selects XV pulses for use as VSG pulses.

0x1D

[23:0]

SCK

VSGMASK_CTL

VSG masking. Overrides settings in field registers when enabled.

[24]

VSGMASK_CTL_EN

0 = disable VSGMASK_CTL bits. VSG masking is controlled by field registers.

1 = enable VSGMASK_CTL bits to control VSG masking.

0x1E

[27]

SCK

UNUSED

Do not access, or set to 0.

0x1F

[0]

0x01

SCK

HCNT14_EN

1 = enable 14-bit H-counter.

[1]

0x01

PBLK_MASK_EN

1 = disable clamp operation if PBLK is active at the same time as CLPOB.

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