PIC18F1220ESLASHPQTP datasheet(16/308 Pages) MICROCHIP

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PIC18F1220/1320

DS39605F-page 14

2.6

Internal Oscillator Block

The PIC18F1220/1320 devices include an internal

oscillator block, which generates two different clock

signals; either can be used as the system’s clock

source. This can eliminate the need for external

oscillator circuits on the OSC1 and/or OSC2 pins.

The main output (INTOSC) is an 8 MHz clock source,

which can be used to directly drive the system clock. It

also drives a postscaler, which can provide a range of

clock frequencies from 125 kHz to 4 MHz. The

INTOSC output is enabled when a system clock

frequency from 125 kHz to 8 MHz is selected.

The other clock source is the internal RC oscillator

(INTRC), which provides a 31 kHz output. The INTRC

oscillator is enabled by selecting the internal oscillator

block as the system clock source, or when any of the

following are enabled:

• Power-up Timer

• Fail-Safe Clock Monitor

• Watchdog Timer

• Two-Speed Start-up

These features are discussed in greater detail in

Section 19.0 “Special Features of the CPU”.

The clock source frequency (INTOSC direct, INTRC

direct or INTOSC postscaler) is selected by configuring

the IRCF bits of the OSCCON register (Register 2-2).

2.6.1

INTIO MODES

Using the internal oscillator as the clock source can

eliminate the need for up to two external oscillator pins,

which can then be used for digital I/O. Two distinct

configurations are available:

• In INTIO1 mode, the OSC2 pin outputs FOSC/4,

while OSC1 functions as RA7 for digital input and

output.

• In INTIO2 mode, OSC1 functions as RA7 and

OSC2 functions as RA6, both for digital input and

output.

2.6.2

INTRC OUTPUT FREQUENCY

The internal oscillator block is calibrated at the factory

to produce an INTOSC output frequency of 8.0 MHz

(see Table 22-6). This changes the frequency of the

INTRC source from its nominal 31.25 kHz. Peripherals

and features that depend on the INTRC source will be

affected by this shift in frequency.

Once set during factory calibration, the INTRC

frequency will remain within ±2% as temperature and

VDD change across their full specified operating

ranges.

2.6.3

OSCTUNE REGISTER

The internal oscillator’s output has been calibrated at

the factory, but can be adjusted in the user’s applica-

tion. This is done by writing to the OSCTUNE register

(Register 2-1). The tuning sensitivity is constant

throughout the tuning range.

When the OSCTUNE register is modified, the INTOSC

and INTRC frequencies will begin shifting to the new

frequency. The INTRC clock will reach the new

frequency

within

8 clock

cycles

(approximately

8* 32

μs = 256 μs). The INTOSC clock will stabilize

within 1 ms. Code execution continues during this shift.

There is no indication that the shift has occurred.

Operation of features that depend on the INTRC clock

source frequency, such as the WDT, Fail-Safe Clock

Monitor and peripherals, will also be affected by the

change in frequency.

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