PIC18F1220ESLASHPQTP datasheet(49/308 Pages) MICROCHIP

49 / 308 page

DS39605F-page 47

PIC18F1220/1320

5.8

Look-up Tables

Look-up tables are implemented two ways:

• Computed GOTO

• Table Reads

5.8.1

COMPUTED GOTO

A computed GOTO is accomplished by adding an offset

to the program counter (see Example 5-4).

A look-up table can be formed with an ADDWF

PCL

instruction and a group of RETLW 0xnn instructions.

WREG is loaded with an offset into the table before

executing a call to that table. The first instruction of the

called routine is the ADDWF PCL instruction. The next

instruction executed will be one of the RETLW 0xnn

instructions, that returns the value 0xnn to the calling

function.

The offset value (in WREG) specifies the number of

bytes that the program counter should advance and

should be multiples of 2 (LSB = 0).

In this method, only one data byte may be stored in

each instruction location and room on the return

address stack is required.

EXAMPLE 5-4:

COMPUTED GOTO USING

AN OFFSET VALUE

5.8.2

TABLE READS/TABLE WRITES

A better method of storing data in program memory

allows two bytes of data to be stored in each instruction

location.

Look-up table data may be stored two bytes per pro-

gram word by using table reads and writes. The Table

Pointer (TBLPTR) register specifies the byte address

and the Table Latch (TABLAT) register contains the

data that is read from or written to program memory.

Data is transferred to/from program memory, one byte

at a time.

The table read/table write operation is discussed

further in Section 6.1 “Table Reads and Table

Writes”.

5.9

Data Memory Organization

The data memory is implemented as static RAM. Each

allowing up to 4096 bytes of data memory. Figure 5-6

shows

the

data

memory

organization

for

the

PIC18F1220/1320 devices.

The data memory map is divided into as many as

16 banks that contain 256 bytes each. The lower 4 bits

of the Bank Select Register (BSR<3:0>) select which

bank will be accessed. The upper 4 bits for the BSR are

not implemented.

The data memory contains Special Function Registers

(SFR) and General Purpose Registers (GPR). The

SFRs are used for control and status of the controller

and peripheral functions, while GPRs are used for data

storage and scratch pad operations in the user’s appli-

cation. The SFRs start at the last location of Bank 15

(FFFh) and extend towards F80h. Any remaining space

beyond the SFRs in the Bank may be implemented as

GPRs. GPRs start at the first location of Bank 0 and

grow upwards. Any read of an unimplemented location

will read as ‘0’s.

The entire data memory may be accessed directly or

indirectly. Direct addressing may require the use of the

BSR register. Indirect addressing requires the use of a

File Select Register (FSRn) and a corresponding Indi-

rect File Operand (INDFn). Each FSR holds a 12-bit

address value that can be used to access any location

in the Data Memory map without banking. See

Section 5.12 “Indirect Addressing, INDF and FSR

Registers” for indirect addressing details.

The instruction set and architecture allow operations

across all banks. This may be accomplished by indirect

addressing or by the use of the MOVFF instruction. The

MOVFF

instruction is a two-word/two-cycle instruction

that moves a value from one register to another.

To ensure that commonly used registers (SFRs and

select GPRs) can be accessed in a single cycle,

regardless of the current BSR values, an Access Bank

is implemented. A segment of Bank 0 and a segment of

Bank 15 comprise the Access RAM. Section 5.10

“Access Bank” provides a detailed description of the

Access RAM.

5.9.1

GENERAL PURPOSE

Enhanced MCU devices may have banked memory in

the GPR area. GPRs are not initialized by a Power-on

Reset and are unchanged on all other Resets.

Data RAM is available for use as GPR registers by all

instructions. The second half of Bank 15 (F80h to

FFFh) contains SFRs. All other banks of data memory

contain GPRs, starting with Bank 0.

MOVFW

OFFSET

CALL

TABLE

ORG

0xnn00

TABLE

ADDWF

PCL

RETLW

0xnn

RETLW

0xnn

RETLW

0xnn

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