PIC18F1220ESLASHPQTP datasheet(91/308 Pages) MICROCHIP

91 / 308 page

DS39605F-page 89

PIC18F1220/1320

FIGURE 10-6:

MCLR/VPP/RA5 PIN BLOCK DIAGRAM

TABLE 10-1:

PORTA FUNCTIONS

TABLE 10-2:

SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

MCLR/VPP/RA5

Data Bus

RD PORTA

RD LATA

Schmitt

Trigger

MCLRE

RD TRISA

Latch

Filter

Low-Level

MCLR Detect

High-Voltage Detect

Internal MCLR

Name

Bit#

Buffer

Function

RA0/AN0

bit 0

Input/output port pin or analog input.

RA1/AN1/LVDIN

bit 1

Input/output port pin, analog input or Low-Voltage Detect input.

RA2/AN2/VREF-

bit 2

Input/output port pin, analog input or VREF-.

RA3/AN3/VREF+

bit 3

Input/output port pin, analog input or VREF+.

RA4/T0CKI

bit 4

Input/output port pin or external clock input for Timer0.

Output is open-drain type.

MCLR/VPP/RA5

bit 5

Master Clear input or programming voltage input (if MCLR is enabled); input

only port pin or programming voltage input (if MCLR is disabled).

OSC2/CLKO/RA6

bit 6

OSC2, clock output or I/O pin.

OSC1/CLKI/RA7

bit 7

OSC1, clock input or I/O pin.

Legend: TTL = TTL input, ST = Schmitt Trigger input

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

POR, BOR

Value on

all other

Resets

PORTA

RA7(1)

RA6(1)

RA5(2)

RA4

RA3

RA2

RA1

RA0

xx0x 0000 uu0u 0000

LATA

LATA7(1)

LATA6(1)

—

LATA Data Output Register

xx-x xxxx uu-u uuuu

TRISA

TRISA7(1) TRISA6(1)

—

PORTA Data Direction Register

11-1 1111 11-1 1111

ADCON1

—

PCFG6

PCFG5

PCFG4

PCFG3

PCFG2

PCFG1

PCFG0 -000 0000 -000 0000

Legend:

= unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.

Note 1:

RA7:RA6 and their associated latch and data direction bits are enabled as I/O pins based on oscillator

configuration; otherwise, they are read as ‘0’.

RA5 is an input only if MCLR is disabled.

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