PIC18F1220ESLASHPQTP datasheet(69/308 Pages) MICROCHIP

69 / 308 page

DS39605F-page 67

PIC18F1220/1320

7.0

DATA EEPROM MEMORY

The data EEPROM is readable and writable during

normal operation over the entire VDD range. The data

memory is not directly mapped in the register file

space. Instead, it is indirectly addressed through the

Special Function Registers (SFR).

There are four SFRs used to read and write the

program and data EEPROM memory. These registers

are:

• EECON1

• EECON2

• EEDATA

• EEADR

The EEPROM data memory allows byte read and write.

When interfacing to the data memory block, EEDATA

holds the 8-bit data for read/write and EEADR holds the

address of the EEPROM location being accessed.

These devices have 256 bytes of data EEPROM with

an address range from 00h to FFh.

The EEPROM data memory is rated for high erase/

write cycle endurance. A byte write automatically

erases the location and writes the new data (erase-

before-write). The write time is controlled by an on-chip

timer. The write time will vary with voltage and

temperature, as well as from chip to chip. Please

refer to parameter D122 (Table 22-1 in Section 22.0

“Electrical Characteristics”) for exact limits.

7.1

EEADR

The address register can address 256 bytes of data

EEPROM.

7.2

EECON1 and EECON2 Registers

EECON1 is the control register for memory accesses.

EECON2 is not a physical register. Reading EECON2

will read all ‘0’s. The EECON2 register is used

exclusively in the memory write and erase sequences.

Control bit, EEPGD, determines if the access will be to

program or data EEPROM memory. When clear,

operations will access the data EEPROM memory.

When set, program memory is accessed.

Control bit, CFGS, determines if the access will be to

the configuration registers or to program memory/data

EEPROM memory. When set, subsequent operations

access configuration registers. When CFGS is clear,

the EEPGD bit selects either program Flash or data

EEPROM memory.

The WREN bit enables and disables erase and write

operations. When set, erase and write operations are

allowed. When clear, erase and write operations are

disabled – the WR bit cannot be set while the WREN bit

is clear. This mechanism helps to prevent accidental

writes to memory due to errant (unexpected) code

execution.

Firmware should keep the WREN bit clear at all times,

except when starting erase or write operations. Once

firmware has set the WR bit, the WREN bit may be

cleared. Clearing the WREN bit will not affect the

operation in progress.

The WRERR bit is set when a write operation is

interrupted by a Reset. In these situations, the user can

check the WRERR bit and rewrite the location. It is

necessary to reload the data and address registers

(EEDATA and EEADR), as these registers have

cleared as a result of the Reset.

Control bits, RD and WR, start read and erase/write

operations, respectively. These bits are set by firmware

and cleared by hardware at the completion of the

operation.

The RD bit cannot be set when accessing program

memory (EEPGD = 1). Program memory is read using

table read instructions. See Section 6.1 “Table Reads

and Table Writes” regarding table reads.

Note:

Interrupt flag bit, EEIF in the PIR2 register,

is set when write is complete. It must be

cleared in software.

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