PIC18F1220ESLASHPQTP datasheet(29/308 Pages) MICROCHIP

29 / 308 page

DS39605F-page 27

PIC18F1220/1320

3.4.3

RC_RUN MODE

In RC_RUN mode, the CPU and peripherals are

clocked from the internal oscillator block using the

INTOSC multiplexer and the primary clock is shut

down. When using the INTRC source, this mode pro-

vides the best power conservation of all the Run

modes, while still executing code. It works well for user

applications which are not highly timing sensitive, or do

not require high-speed clocks at all times.

If the primary clock source is the internal oscillator

block (either of the INTIO1 or INTIO2 oscillators), there

are no distinguishable differences between PRI_RUN

and RC_RUN modes during execution. However, a

clock switch delay will occur during entry to and exit

from RC_RUN mode. Therefore, if the primary clock

source is the internal oscillator block, the use of

RC_RUN mode is not recommended.

This mode is entered by clearing the IDLEN bit, setting

SCS1 (SCS0 is ignored) and executing a SLEEP

instruction. The IRCF bits may select the clock

frequency before the SLEEP instruction is executed.

When the clock source is switched to the INTOSC

multiplexer (see Figure 3-10), the primary oscillator is

shut down and the OSTS bit is cleared.

The IRCF bits may be modified at any time to immedi-

ately change the system clock speed. Executing a

SLEEP

instruction is not required to select a new clock

frequency from the INTOSC multiplexer.

If the IRCF bits are all clear, the INTOSC output is not

enabled and the IOFS bit will remain clear; there will be

no indication of the current clock source. The INTRC

source is providing the system clocks.

If the IRCF bits are changed from all clear (thus,

enabling the INTOSC output), the IOFS bit becomes

set after the INTOSC output becomes stable. Clocks to

the system continue while the INTOSC source

stabilizes, in approximately 1 ms.

If the IRCF bits were previously at a non-zero value

before the SLEEP instruction was executed and the

INTOSC source was already stable, the IOFS bit will

remain set.

When a wake event occurs, the system continues to be

clocked from the INTOSC multiplexer while the primary

clock is started. When the primary clock becomes

ready, a clock switch to the primary clock occurs (see

Figure 3-8). When the clock switch is complete, the

IOFS bit is cleared, the OSTS bit is set and the primary

clock is providing the system clock. The IDLEN and

SCS bits are not affected by the wake-up. The INTRC

source will continue to run if either the WDT or the

Fail-Safe Clock Monitor is enabled.

FIGURE 3-10:

TIMING TRANSITION TO RC_RUN MODE

Note:

Caution should be used when modifying a

single IRCF bit. If VDD is less than 3V, it is

possible to select a higher clock speed

than is supported by the low VDD.

Improper device operation may result if

the VDD/FOSC specifications are violated.

OSC1

Peripheral

Program

INTRC

Counter

Clock

CPU

Clock

PC + 2

Clock Transition

PC + 4

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