PIC18F1220ESLASHPQTP datasheet(32/308 Pages) MICROCHIP

32 / 308 page

PIC18F1220/1320

DS39605F-page 30

3.5.2

EXIT BY RESET

Normally, the device is held in Reset by the Oscillator

Start-up Timer (OST) until the primary clock (defined in

Configuration Register 1H) becomes ready. At that

time, the OSTS bit is set and the device begins

executing code.

Code execution can begin before the primary clock

becomes ready. If either the Two-Speed Start-up (see

Section 19.3 “Two-Speed Start-up”) or Fail-Safe

Clock Monitor (see Section 19.4 “Fail-Safe Clock

Monitor”) are enabled in Configuration Register 1H,

the device may begin execution as soon as the Reset

source has cleared. Execution is clocked by the

INTOSC multiplexer driven by the internal oscillator

block. Since the OSCCON register is cleared following

all Resets, the INTRC clock source is selected. A

higher speed clock may be selected by modifying the

IRCF bits in the OSCCON register. Execution is

clocked by the internal oscillator block until either the

primary clock becomes ready, or a power managed

mode is entered before the primary clock becomes

ready; the primary clock is then shut down.

3.5.3

EXIT BY WDT TIME-OUT

A WDT time-out will cause different actions, depending

on which power managed mode the device is in when

the time-out occurs.

If the device is not executing code (all Idle modes and

Sleep mode), the time-out will result in a wake from the

power managed mode (see Sections 3.2 through 3.4).

If the device is executing code (all Run modes), the

time-out will result in a WDT Reset (see Section 19.2

“Watchdog Timer (WDT)”).

The WDT timer and postscaler are cleared by

executing a SLEEP or CLRWDT instruction, the loss of a

currently selected clock source (if the Fail-Safe Clock

Monitor is enabled) and modifying the IRCF bits in the

OSCCON register if the internal oscillator block is the

system clock source.

3.5.4

EXIT WITHOUT AN OSCILLATOR

START-UP DELAY

Certain exits from power managed modes do not

invoke the OST at all. These are:

• PRI_IDLE mode, where the primary clock source

is not stopped; or

• the primary clock source is not any of LP, XT, HS

or HSPLL modes.

In these cases, the primary clock source either does

not require an oscillator start-up delay, since it is

already running (PRI_IDLE), or normally does not

require an oscillator start-up delay (RC, EC and INTIO

Oscillator modes).

However, a fixed delay (approximately 10

μs) following

the wake event is required when leaving Sleep and Idle

modes. This delay is required for the CPU to prepare

for execution. Instruction execution resumes on the first

clock cycle following this delay.

3.6

INTOSC Frequency Drift

The factory calibrates the internal oscillator block

output (INTOSC) for 8 MHz (see Table 22-6). However,

this frequency may drift as VDD or temperature

changes, which can affect the controller operation in a

variety of ways.

It is possible to adjust the INTOSC frequency by

modifying

the

value

the

OSCTUNE

(Register 2-1). This has the side effect that the INTRC

clock source frequency is also affected. However, the

features that use the INTRC source often do not require

an exact frequency. These features include the Fail-Safe

Clock Monitor, the Watchdog Timer and the RC_RUN/

RC_IDLE modes when the INTRC clock source is

selected.

Being able to adjust the INTOSC requires knowing

when an adjustment is required, in which direction it

should be made and in some cases, how large a

change is needed. Three examples follow but other

techniques may be used.

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