MPC8349EVVALDB datasheet(27/87 Pages) FREESCALE

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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13

Freescale Semiconductor

Ethernet: Three-Speed Ethernet, MII Management

Figure 12 provides the AC test load for TSEC.

Figure 12. TSEC AC Test Load

Figure 13 shows the MII receive AC timing diagram.

Figure 13. MII Receive AC Timing Diagram

8.2.3

TBI AC Timing Specifications

This section describes the TBI transmit and receive AC timing specifications.

RX_CLK clock rise (20%–80%)

tMRXR

1.0

—

4.0

RX_CLK clock fall time (80%–20%)

tMRXF

1.0

—

4.0

Note:

1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH symbolizes MII receive timing

(MR) with respect to the time data input signals (D) reach the valid state (V) relative to the tMRX clock reference (K) going to

the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with respect to the time data input signals

(D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state or hold time. In general, the clock

reference symbol is based on three letters representing the clock of a particular function. For example, the subscript of tMRX

represents the MII (M) receive (RX) clock. For rise and fall times, the latter convention is used with the appropriate letter:

R (rise) or F (fall).

Table 28. MII Receive AC Timing Specifications (continued)

At recommended operating conditions with LVDD/OVDD of 3.3 V ± 10%.

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

RX_CLK

RXD[3:0]

tMRDXKH

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER

tMRDVKH

Valid Data

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