Networking Silicon — 82541(PI/GI/EI)

27

4.5

Timing Specifications

AC Test Loads for General Output Pins

Symbol

Signal Name

Value

Units

CL

TDO

10

pF

CL

PME#, SDP[3:0]

16

pF

CL

EEDI, EESK

18

pF

CL

LED[3:0]

20

pF

Figure 3. AC Test Loads for General Output Pins

Table 17. PCI Bus Interface Clock Parameters

Symbol

a. Rise and fall times are specified in terms of the edge rate measured in V/ns. This slew rate must be met across the

minimum peak-to-peak portion of the clock waveform as shown.

PCI 66 MHz

PCI 33 MHz

Units

Min

Max

Min

Max

TCYC

CLK cycle time

15

30

30

ns

TH

CLK high time

6

11

ns

TL

CLK low time

6

11

ns

CLK slew rate

1.5

4

1

4

V/ns

b. The minimum RST# slew rate applies only to the rising (de-assertion) edge of the reset signal and ensures that system

noise cannot render a monotonic signal to appear bouncing in the switching range.

50

50

mV/ns

CL