GD82541PI datasheet(12/46 Pages) INTEL

12 / 46 page

82541(PI/GI/EI) — Networking Silicon

3.2.1

PCI Address, Data and Control Signals (44)

Symbol

Type

Name and Function

AD[31:0]

Address and Data. Address and data signals are multiplexed on the same PCI pins. A

bus transaction includes an address phase followed by one or more data phases.

The address phase is the clock cycle when the Frame signal (FRAME#) is asserted

low. During the address phase AD[31:0] contain a physical address (32 bits). For I/O,

this is a byte address, and for configuration and memory, a DWORD address. The

82541(PI/GI/EI) device uses little endian byte ordering.

During data phases, AD[7:0] contain the least significant byte (LSB) and AD[31:24]

contain the most significant byte (MSB).

C/BE#[3:0]

Bus Command and Byte Enables. Bus command and byte enable signals are

multiplexed on the same PCI pins. During the address phase of a transaction, C/

BE#[3:0] define the bus command. In the data phase, C/BE#[3:0] are used as byte

enables. The byte enables are valid for the entire data phase and determine which byte

lanes contain meaningful data.

C/BE[0]# applies to byte 0 (LSB) and C/BE#[3] applies to byte 3 (MSB).

PAR

Parity. The Parity signal is issued to implement even parity across AD[31:0] and C/

BE#[3:0]. PAR is stable and valid one clock after the address phase. During data

phases, PAR is stable and valid one clock after either IRDY# is asserted on a write

transaction or TRDY# is asserted after a read transaction. Once PAR is valid, it remains

valid until one clock after the completion of the current data phase.

When the 82541(PI/GI/EI) controller is a bus master, it drives PAR for address and write

data phases, and as a slave device, drives PAR for read data phases.

FRAME#

STS

Cycle Frame. The Frame signal is driven by the 82541(PI/GI/EI) device to indicate the

beginning and length of a bus transaction.

While FRAME# is asserted, data transfers continue. FRAME# is de-asserted when the

transaction is in the final data phase.

IRDY#

STS

Initiator Ready. Initiator Ready indicates the ability of the 82541(PI/GI/EI) controller

(as a bus master device) to complete the current data phase of the transaction. IRDY#

is used in conjunction with the Target Ready signal (TRDY#). The data phase is

completed on any clock when both IRDY# and TRDY# are asserted.

During the write cycle, IRDY# indicates that valid data is present on AD[31:0]. For a

read cycle, it indicates the master is ready to accept data. Wait cycles are inserted until

both IRDY# and TRDY# are asserted together. The 82541(PI/GI/EI) controller drives

IRDY# when acting as a master and samples it when acting as a slave.

TRDY#

STS

Target Ready. The Target Ready signal indicates the ability of the 82541(PI/GI/EI)

controller (as a selected device) to complete the current data phase of the transaction.

TRDY# is used in conjunction with the Initiator Ready signal (IRDY#). A data phase is

completed on any clock when both TRDY# and IRDY# are sampled asserted.

During a read cycle, TRDY# indicates that valid data is present on AD[31:0]. For a write

cycle, it indicates the target is ready to accept data. Wait cycles are inserted until both

IRDY# and TRDY# are asserted together. The 82541(PI/GI/EI) device drives TRDY#

when acting as a slave and samples it when acting as a master.

STOP#

STS

Stop. The Stop signal indicates the current target is requesting the master to stop the

current transaction. As a slave, the 82541(PI/GI/EI) controller drives STOP# to request

the bus master to stop the transaction. As a master, the 82541(PI/GI/EI) controller

receives STOP# from the slave to stop the current transaction.

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