MPC8536DS datasheet(115/126 Pages) FREESCALE

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Hardware Design Considerations

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

115

This figure shows the PLL power supply filter circuit.

Figure 75. Chip PLL Power Supply Filter Circuit

The AVDD_SRDSn signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock,

the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 76. For maximum

effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn balls to ensure it filters out as much noise

as possible. The ground connection should be near the AVDD_SRDSn balls. The 0.003-µF capacitor is closest to the balls,

followed by the 1-µF capacitor, and finally the 1 ohm resistor to the board supply plane. The capacitors are connected from

AVDD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces

should be kept short, wide and direct.

Figure 76. SerDes PLL Power Supply Filter Circuit

Note the following:

•AVDD should be a filtered version of SVDD.

•

Signals on the SerDes interface are fed from the XVDD power plane.

3.3

Pin States in Deep Sleep State

In all low power mode by default, all input and output pads remain driven as per normal functional operation. The inputs remain

enabled.

The exception is that in Deep Sleep mode, GCR[DEEPSLEEP_Z] can be used to tristate a subset of output pads, and disable

the receivers of input pads as defined in Table 1. See the MPC8536E PowerQUICC III Integrated Processor Reference Manual

for details.

3.4

Decoupling Recommendations

Due to large address and data buses, and high operating frequencies, this chip can generate transient power surges and high

frequency noise in its power supply, especially while driving large capacitive loads. This noise must be prevented from reaching

other components in the chip system, and the chip itself requires a clean, tightly regulated source of power. Therefore, it is

recommended that the system designer place at least one decoupling capacitor at each VDD, TVDD, BVDD, OVDD, GVDD, and

LVDD pin of the chip. These decoupling capacitors should receive their power from separate VDD,TVDD, BVDD, OVDD, GVDD,

and LVDD, and GND power planes in the PCB, utilizing short low impedance traces to minimize inductance. Capacitors must

be placed directly under the chip using a standard escape pattern as much as possible. If some caps are to be placed surrounding

the part it should be routed with short and large trace to minimize the inductance.

VDD

AVDD

2.2 µF

GND

Low ESL Surface Mount Capacitors

2.2 µF 1

0.003 µF

GND

1.0

AVDD - SRDS

1. An 0805 sized capacitor is recommended for system initial bring-up

SnVDD

2.2 µF 1

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