MPC8536DS datasheet(87/126 Pages) FREESCALE

87 / 126 page

Electrical Characteristics

MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

This figure provides the AC test load for the I2C.

Figure 51. I2C AC Test Load

This figure shows the AC timing diagram for the I

2C bus.

Figure 52. I2C Bus AC Timing Diagram

Bus free time between a STOP and START condition

tI2KHDX

1.3

—

μs—

Noise margin at the LOW level for each connected device

(including hysteresis)

VNL

0.1

× OVDD

—V

—

Noise margin at the HIGH level for each connected device

(including hysteresis)

VNH

0.2

× OVDD

—V

—

Note:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I

2C timing

(I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the

high (H) state or setup time. Also, tI2SXKL symbolizes I

2C timing (I2) for the time that the data with respect to the start condition

(S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I

timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. As a transmitter, the chip provides a delay time of at least 300 ns for the SDA signal (referred to the Vihmin of the SCL signal)

to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition. When the

chip acts as the I2C bus master while transmitting, the chip drives both SCL and SDA. As long as the load on SCL and SDA

are balanced, the chip would not cause unintended generation of Start or Stop condition. Therefore, the 300 ns SDA output

delay time is not a concern. For details of the I2C frequency calculation, refer to

Determining the I2C Frequency Divider Ratio

for SCL (AN2919). Note that the I2C Source Clock Frequency is half of the CCB clock frequency for the chip.

3. The maximum tI2DVKH has only to be met if the chip does not stretch the LOW period (tI2CL) of the SCL signal.

4. CB = capacitance of one bus line in pF.

Table 64. I2C AC Electrical Specifications (continued)

All values refer to VIH (min) and VIL (max) levels (see Table 63).

Parameter

Symbol 1

Min

Max

Unit

Notes

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

SDA

SCL

tI2CF

tI2SXKL

tI2CL

tI2CH

tI2DXKL, tI2OVKL

tI2DVKH

tI2SXKL

tI2SVKH

tI2KHKL

tI2PVKH

tI2CR

tI2CF

MPC8536DS датащи(PDF) 87 Page - Freescale Semiconductor, Inc

MPC8536DS датащи(HTML) 87 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL