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MPC8536DS датащи(PDF) 79 Page - Freescale Semiconductor, Inc |
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MPC8536DS датащи(HTML) 79 Page - Freescale Semiconductor, Inc |
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79 / 126 page ![]() Electrical Characteristics MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 79 This figure provides the AC test load for TDO and the boundary-scan outputs. Figure 45. AC Test Load for the JTAG Interface This figure provides the JTAG clock input timing diagram. Figure 46. JTAG Clock Input Timing Diagram This figure provides the TRST timing diagram. Figure 47. TRST Timing Diagram This figure provides the boundary-scan timing diagram. Figure 48. Boundary-Scan Timing Diagram 2.16 Serial ATA (SATA) This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the chip. Note that the external cabled applications or long backplane applications (Gen1x & Gen2x) are not supported. Output Z0 = 50 Ω OVDD/2 RL = 50 Ω JTAG tJTKHKL tJTGR External Clock VM VM VM tJTG tJTGF VM = Midpoint Voltage (OVDD/2) TRST VM = Midpoint Voltage (OVDD/2) VM VM tTRST VM VM tJTDVKH tJTDXKH Boundary Data Outputs JTAG External Clock Boundary Data Inputs Output Data Valid tJTKLDX tJTKLDV Input Data Valid VM = Midpoint Voltage (OVDD/2) |
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