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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MPC8536DS датащи(PDF) 55 Page - Freescale Semiconductor, Inc |
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MPC8536DS датащи(HTML) 55 Page - Freescale Semiconductor, Inc |
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55 / 126 page  Electrical Characteristics MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 Freescale Semiconductor 55 When operating in SGMII mode, the eTSEC EC_GTX_CLK125 clock is not required for this port. Instead, SerDes reference clock is required on SD2_REF_CLK and SD2_REF_CLK pins. 2.9.3.1 DC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK The characteristics and DC requirements of the separate SerDes reference clock are described in Section 2.20, “High-Speed Serial Interfaces.” 2.9.3.2 AC Requirements for SGMII SD2_REF_CLK and SD2_REF_CLK This table lists the SGMII SerDes reference clock AC requirements. Please note that SD2_REF_CLK and SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread spectrum clock source. Table 38. SD2_REF_CLK and SD2_REF_CLK AC Requirements Symbol Parameter Description Min Typical Max Units Notes tREF REFCLK cycle time — 10 (8) — ns 1 tREFCJ REFCLK cycle-to-cycle jitter. Difference in the period of any two adjacent REFCLK cycles — — 100 ps — tREFPJ Phase jitter. Deviation in edge location with respect to mean edge location –50 — 50 ps 2,3 Notes: 1. 8 ns applies only when 125 MHz SerDes2 reference clock frequency is selected via cfg_srds_sgmii_refclk during POR. 2. In a frequency band from 150 kHz to 15 MHz, at BER of 10E-12. 3. Total peak-to-peak deterministic jitter “Dj” should be less than or equal to 50 ps. |
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