MPC8536DS datasheet(78/126 Pages) FREESCALE

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MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Electrical Characteristics

Freescale Semiconductor

2.15.2

JTAG AC Electrical Specifications

This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the chip.

This table provides the JTAG AC timing specifications as defined in the following figures.

Input current

(VIN

1 = 0 V or V

IN = VDD)

IIN

—±5

μA

High-level output voltage

(OVDD = min, IOH = -2 mA)

VOH

2.4

—

Low-level output voltage

(OVDD = min, IOL = 2 mA)

VOL

—0.4

Notes:

1. Note that the symbol VIN, in this case, represents the OVIN.

Table 58. JTAG AC Timing Specifications (Independent of SYSCLK)

At recommended operating conditions (see Table 3).

Parameter

Symbol 1

Min

Max

Unit

Notes

JTAG external clock frequency of operation

fJTG

33.3

MHz

—

JTAG external clock cycle time

t JTG

—

JTAG external clock pulse width measured at 1.4 V

tJTKHKL

—

JTAG external clock rise and fall times

tJTGR & tJTGF

—

TRST assert time

tTRST

—

Input setup times:

tJTDVKH

4—

Input hold times:

tJTDXKH

—

Output Valid times:

tJTKLDV

—10

Output hold times:

tJTKLDX

0—

Notes:

1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG

device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference

(K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input

signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock

reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3.) The output timings are measured at the pins. All output timings assume a purely resistive 50-

Ω load. Time-of-flight delays

must be added for trace lengths, vias, and connectors in the system.

Table 57. JTAG DC Electrical Characteristics (continued)

Parameter

Symbol 1

Min

Max

Unit

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