MPC8536DS datasheet(110/126 Pages) FREESCALE

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MPC8536E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Electrical Characteristics

Freescale Semiconductor

110

2.23.6

Frequency Options

2.23.6.1

SYSCLK to Platform Frequency Options

This table shows the expected frequency values for the platform frequency when using a CCB clock to SYSCLK ratio in

comparison to the memory bus clock speed.

2.23.6.2

Minimum Platform Frequency Requirements for High-speed Interfaces

Section 4.4.3.8 “SerDes1 I/O Port Selection” and Section 4.4.3.9 “SerDes2 I/O Port Selection” of the MPC8536E

PowerQUICC III Integrated Host Processor Family Reference Manual, describes various high-speed interface configuration

options. Note that the CCB clock frequency must be considered for proper operation of such interfaces as described below.

For proper PCI Express operation, the CCB clock frequency must be equal or greater than:

See Section 18.1.3.2, “Link Width,” of the MPC8536E PowerQUICC III Integrated Host Processor Family Reference Manual,

for PCI Express interface width details. Note that the “PCI Express link width” in the above equation refers to the negotiated

link width as the result of PCI Express link training, which may or may not be the same as the link width POR selection.

2.24

Thermal

This section describes the thermal specifications of the chip.

Table 78. Frequency Options of SYSCLK with Respect to Memory Bus Speeds

CCB to

SYSCLK Ratio

SYSCLK (MHz)

33.33

41.66

66.66

100

111

133.33

Platform /CCB Frequency (MHz)

333

400

333

400

444

533

333

415

500

400

500

333

533

333

417

400

500

533

527 MHz

PCI Express link width

()

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