AD9735BBC datasheet(30/72 Pages) AD

30 / 72 page

AD9734/AD9735/AD9736

Rev. A | Page 30 of 72

SPI REGISTER DETAILS

Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Reset value for write registers

in bold text.

MODE REGISTER (REG. 0)

ADDR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00

MODE

SDIO_DIR

LSB/MSB

RESET

LONG_INS

2× MODE

FIFO MODE

DATAFRMT

Table 10. Mode Register Bit Descriptions

Bit Name

Read/Write

Description

SDIO_DIR

WRITE

0, input only per SPI standard.

1, bidirectional per SPI standard.

LSB/MSB

WRITE

0, MSB first per SPI standard.

1, LSB first per SPI standard.

NOTE: Only change LSB/MSB order in single-byte instructions to avoid erratic behavior due to bit

order errors.

RESET

WRITE

0, execute software reset of SPI and controllers, reload default register values except Registers 0x00

and 0x04.

1, set software reset, write 0 on the next (or any following) cycle to release the reset.

LONG_INS

WRITE

0, short (single-byte) instruction word.

1, long (two-byte) instruction word, not necessary since the maximum internal address is REG31

(0x1F).

2×_MODE

WRITE

0, disable 2× interpolation filter.

1, enable 2× interpolation filter.

FIFO_MODE

WRITE

0, disable FIFO synchronization.

1, enable FIFO synchronization.

DATAFRMT

WRITE

0, signed input DATA with midscale = 0x0000.

1, unsigned input DATA with midscale = 0x2000.

WRITE

0, enable LVDS Receiver, DAC, and clock circuitry.

1, power down LVDS Receiver, DAC, and clock circuitry.

INTERRUPT REQUEST REGISTER (IRQ) (REG. 1)

ADDR

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x01

IRQ

LVDS

SYNC

CROSS

RESERVED

IE_LVDS

IE_SYNC

IE_CROSS

RESERVED

Table 11. Interrupt Register Bit Descriptions

Bit Name

Read/Write

Description

LVDS

WRITE

Don’t care.

READ

0, no active LVDS receiver interrupt.

1, interrupt in LVDS receiver occurred.

SYNC

WRITE

Don’t care.

READ

0, no active SYNC logic interrupt.

1, interrupt in SYNC logic occurred.

CROSS

WRITE

Don’t care.

READ

0, no active CROSS logic interrupt.

1, interrupt in CROSS logic occurred.

IE_LVDS

WRITE

0, reset LVDS receiver interrupt and disable future LVDS receiver interrupts.

1, enable LVDS receiver interrupt to activate IRQ pin.

IE_SYNC

WRITE

0, reset SYNC logic interrupt and disable future SYNC logic interrupts.

1, enable SYNC logic interrupt to activate IRQ pin.

IE_CROSS

WRITE

0, reset CROSS logic interrupt and disable future CROSS logic interrupts.

1, enable CROSS logic interrupt to activate IRQ pin.

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