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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9735BBC датащи(PDF) 6 Page - Analog Devices |
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AD9735BBC датащи(HTML) 6 Page - Analog Devices |
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6 / 72 page  AD9734/AD9735/AD9736 Rev. A | Page 6 of 72 DIGITAL SPECIFICATIONS AVDD33 = DVDD33 = 3.3 V, CVDD18 = DVDD18 = 1.8 V, maximum sample rate, IFS = 20 mA, 1× mode, 25 Ω, 1% balanced load, unless otherwise noted. LVDS drivers and receivers are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. Parameter Min Typ Max Unit LVDS DATA INPUT (DB[13:0]+, DB[13:0]−) DB+ = VIA, DB− = VIB Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold, VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV Receiver Differential Input Impedance, RIN 80 120 Ω LVDS Input Rate 1200 MSPS LVDS Minimum Data Valid Period (tMDE) 344 ps LVDS CLOCK INPUT (DATACLK_IN+, DATACLK_IN−) DATACLK_IN+ = VIA, DATACLK_IN− = VIB Input Voltage Range, VIA or VIB 825 1575 mV Input Differential Threshold,1 VIDTH −100 +100 mV Input Differential Hysteresis, VIDTHH − VIDTHL 20 mV Receiver Differential Input Impedance, RIN 80 120 Ω Maximum Clock Rate 600 MHz LVDS CLOCK OUTPUT (DATACLK_OUT+, DATACLK_ OUT−) DATACLK_OUT+ = Voa, DATACLK_OUT− = Vob 100 Ω Termination Output Voltage High, VOA or VOB 1375 mV Output Voltage Low, VOA or VOB 1025 mV Output Differential Voltage, |VOD| 150 200 250 mV Output Offset Voltage, VOS 1150 1250 mV Output Impedance, Single-Ended, RO 80 100 120 Ω RO Mismatch Between A and B, ΔRO 10 % Change in |VOD| Between 0 and 1, | ΔVOD| 25 mV Change in VOS Between 0 and 1, ΔVOS 25 mV Output Current—Driver Shorted to Ground, ISA, ISB 20 mA Output Current—Drivers Shorted Together, ISAB 4 mA Power-Off Output Leakage, |IXA|, |IXB| 10 mA Maximum Clock Rate 600 MHz DAC CLOCK INPUT (CLK+, CLK−) Input Voltage Range, CLK− or CLK+ 0 800 Differential Peak-to-Peak Voltage 400 800 1600 mV Common-Mode Voltage 300 400 500 mV Maximum Clock Rate 1200 MHz SERIAL PERIPHERAL INTERFACE Maximum Clock Rate (fSCLK, 1/tSCLK) 20 MHz Minimum Pulse Width High, tPWH 20 ns Minimum Pulse Width Low, tPWL 20 ns Minimum SDIO and CSB to SCLK Setup, tDS 10 ns Minimum SCLK to SDIO Hold, tDH 5 ns Maximum SCLK to Valid SDIO and SDO, tDV 20 ns Minimum SCLK to Invalid SDIO and SDO, tDNV 5 ns |
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