AD9735BBC datasheet(53/72 Pages) AD

53 / 72 page

AD9734/AD9735/AD9736

Rev. A | Page 53 of 72

DAC DATA SOURCES

The circuit shown in Figure 96 allows optimum data alignment

when running the AD973x at full speed. This circuit can be

easily implemented in the FPGA or ASIC used to drive the

digital input. It is important to use the DATACLK_OUT signal

because it helps to cancel some of the timing errors. In this

configuration, DATACLK_OUT generates the DDR LVDS

DATACLK_IN to drive the AD973x. The circuit aligns the

DATACLK_IN and the digital input data (DB<13:0>) as

required by the AD973x. The LVDS controller in the AD973x

uses DATACLK_IN to generate the internal DSS to capture the

incoming data in the center of the valid data window.

MUX

DATACLK_OUT

FROM AD9736 (DDR)

DATACLK_IN

TO AD9736 (DDR)

DB(13:0) TO AD9736

DATA SOURCE

LOGIC 0

LOGIC 1

DATA2

DATA1

Figure 96. Recommended FPGA/ASIC Configuration for Driving AD9736

Digital Inputs, 1× Mode

DATA1

DATA2

DATACLK_OUT+

DATACLK_IN+

Figure 97. FPGA/ASIC Timing for Driving AD973x Digital Inputs, 1× Mode

To operate in 2× mode, the circuit in Figure 96 must be

modified to include a divide-by-2 block in the path of

DATACLK_OUT. Without this additional divider, the data and

DATACLK_IN runs 2× too fast. DATACLK_OUT is always

DACCLK/2.

Contact FPGA vendors directly regarding the maximum output

data rates supported by their products.

MUX

DATACLK_OUT

FROM AD9736 (DDR)

DATACLK_IN

TO AD9736 (DDR)

DB(13:0) TO AD9736

DATA SOURCE

LOGIC 1

LOGIC 0

DATA2

DATA1

÷2

Figure 98. Recommended FPGA/ASIC Configuration for Driving AD9736

Digital Inputs, 2× Mode

CLK_OUT+/2

DATA2

DATA1

DATACLK_OUT+

DATACLK_IN+

Figure 99. FPGA/ASIC Timing for Driving AD973x Digital Inputs, 2× Mode

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