AD9735BBC datasheet(54/72 Pages) AD

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AD9734/AD9735/AD9736

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INPUT DATA TIMING

The AD973x is intended to operate with the LVDS and sync

controllers running to compensate for timing drift due to

voltage and temperature variations. In this mode, the key to

correct data capture is to present valid data for a minimum

amount of time. The AD973x minimum valid data time is

measured by increasing the input data rate to the point of

failure. The nominal supply voltages are used and the

temperature is set to the worst case of 85°C. The input

data is verified via the BIST signature registers, because the

DAC output does not run as fast as the input data logic. The

following example explains how the minimum data valid

period is calculated for the typical performance case.

These factors must be considered in determining the minimum

valid data window at the receiver input:

•

Data rise and fall times: 100 ps (rise + fall)

•

Internal clock jitter: 10 ps

(DATACLK_OUT + DATACLK_IN)

•

Bit-to-bit skew: 50 ps

•

Bit-to-DATACLK_IN skew: 50 ps

•

Internal data sampling signal resolution: 80 ps

For nominal silicon, the BIST typically indicates failure at

2.15 GSPS or a DACCLK period of 465 ps. The valid data

window is calculated by subtracting all the other variables

from the total data period:

Minimum Data Valid Time = DACCLK Period − Data Rise −

Data Fall − Jitter − Bit-to-Bit Skew − Bit-to-DATACLK_IN Skew

− Data Sampling Signal Resolution

For the 400 mV p-p LVDS signal case:

Minimum Data Valid = 465 ps − 100 ps − 10 ps − 50 ps −

80 ps = 465 ps − 240 ps = 225 ps

For correct data capture, the input data must be valid for 225 ps.

Slower edges, more jitter, or more skew require an increase in

the clock period to maintain the minimum data valid period.

Table 27 shows the typical minimum data valid period (tMDE) for

400 mV p-p differential and 250 mV p-p differential LVDS swings.

The ability of the AD973x to capture incoming data is

dependent on the speed of the silicon, which varies from lot to

lot. The typical (or average) silicon speed operates with data

that is valid for 225 ps at 85°C. Statistically, the worst extreme

for slow silicon may require up to a 344 ps valid data period, as

specified in Table 2.

Table 27. Typical Minimum Data Valid Times

Differential Input

Voltage

BIST

Max fCLK

Min Clock

Period

Typ Min Data

Valid at Receiver

400 mV

2.15 GHz

465 ps

225 ps

250 mV

2.00 GHz

500 ps

260 ps

At 1.2 GHz, the typical 400 mV p-p minimum data valid period

of 225 ps leaves 608 ps for external factors. Under the same

conditions, the worst expected minimum data valid period of

344 ps leaves 489 ps for external data uncertainty.

The 100 mV LVDS VOD threshold test is a dc test to verify that

the input logic state changes. It does not indicate the operating

speed. The ability of the receiver to recover the data depends on

the input signal overdrive. With a 250 mV input, there is a

150 mV overdrive, and with a 400 mV signal, there is a 300 mV

overdrive. The relationship between overdrive level and timing

is very nonlinear. Higher levels of overdrive result in smaller

minimum valid data windows.

For typical silicon, decreasing the LVDS swing from 400 mV p-p

to 250 mV p-p requires the minimum data valid period to

increase by 15%. This is illustrated in Figure 100.

225ps

400mV

260ps

250mV

Figure 100. Typical Minimum Valid Data Time (tMDE) vs. LVDS Swing

The minimum valid data window changes with temperature,

voltage, and process. The maximum value presented in the

specification table was determined from a 6σ distribution in the

worst-case conditions.

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