AD9735BBC datasheet(38/72 Pages) AD

38 / 72 page

AD9734/AD9735/AD9736

Rev. A | Page 38 of 72

INSTRUCTION BIT 6

INSTRUCTION BIT 7

CSB

SCLK

SDIO

tDS

tDH

tPWH

tPWL

tSCLK

Figure 73. Timing Diagram for SPI Register Write

tDV

tDNV

CSB

SCLK

SDIO

Figure 74. Timing Diagram for SPI Register Read

After the last instruction bit is written to the SDIO pin, the

driving signal must be set to a high impedance in time for the

bus to turn around. The serial output data from the AD973x is

enabled by the falling edge of SCLK. This causes the first output

data bit to be shorter than the remaining data bits, as shown in

Figure 74.

To assure proper reading of data, read the SDIO or SDO pin

prior to changing the SCLK from low to high. Due to the more

complex multibyte protocol, multiple AD973x devices cannot

be daisy-chained on the SPI bus. Multiple DACs should be

controlled by independent CSB signals.

PIN MODE OPERATION

When the PIN_MODE input (Pin L1) is set high, the SPI port is

disabled. The SPI port pins are remapped, as shown in Table 21.

The function of these pins is described in Table 22. The remain-

ing PIN_MODE register settings are shown in Table 9.

Table 21. SPI_MODE vs. PIN_MODE Inputs

Pin Number

PIN_MODE = 0

PIN_MODE = 1

E13

IRQ

UNSIGNED

F13

CSB

2×

G13

SCLK

FSC0

E14

RESET

F14

SDIO

FIFO

G14

SDO

FSC1

Table 22. PIN_MODE Input Functions

Mnemonic

Function

UNSIGNED

0, twos complement input data format

1, unsigned input data format

2×

0, interpolation disabled

1, interpolation = 2× enabled

FSC1, FSC0

00, sleep mode

01, 10 mA full-scale output current

10, 20 mA full-scale output current

11, 30 mA full-scale output current

0, chip enabled

1, chip in power-down state

FIFO

0, input FIFO disabled

1, input FIFO enabled

Care must be taken when using PIN_MODE because only the

control bits shown in Table 22 can be changed. If the remaining

PIN_MODE cannot be used. If the FIFO is enabled, the

controller clock must be less than 10 MHz. This limits the DAC

clock to 160 MHz.

RESET OPERATION

The RESET pin forces all SPI register contents to their default

values (see Table 9), which places the DAC in a known state.

The software reset bit forces all SPI register contents, except

Reg. 0 and Reg. 4, to their default values.

The internal reset signal is derived from a logical OR operation

on the RESET pin state and from the software reset state. This

internal reset signal drives all SPI registers to their default

values, except Reg. 0 and Reg. 4, which are unaffected. The data

registers are not affected by either reset.

The software reset is asserted by writing 1 to Reg. 0, Bit 5. It

may be cleared on the next SPI write cycle or a later write cycle.

PROGRAMMING SEQUENCE

The AD973x registers should be programmed in this order:

Reset hardware.

Make changes to SPI port configuration, if necessary.

Input format, if unsigned.

Interpolation, if in 2× mode.

Calibrate and set the LVDS controller.

Enable the FIFO.

Calibrate and set the sync controller.

Step 1 through Step 4 are required, while Step 5 through Step 7

are optional. The LVDS controller can help assure proper data

reception in the DAC with changes in temperature and voltage.

The sync controller manages the FIFO to assure proper transfer

of the received data to the DAC core with changes in

temperature and voltage. The DAC is intended to operate with

both controllers active unless data and clock alignment is

managed externally.

AD9735BBC датащи(PDF) 38 Page - Analog Devices

AD9735BBC датащи(HTML) 38 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

датащи скачать

ссылки URL