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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LCMXO2-640ZE-3TG100C датащи(PDF) 24 Page - Lattice Semiconductor |
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LCMXO2-640ZE-3TG100C датащи(HTML) 24 Page - Lattice Semiconductor |
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24 / 106 page  2-20 Architecture MachXO2 Family Data Sheet More information on the input gearbox is available in TN1203, Implementing High-Speed Interfaces with MachXO2 Devices. Output Gearbox Each PIC on the top edge has a built-in 8:1 output gearbox. Each of these output gearboxes may be programmed as a 7:1 serializer or as one ODDRX4 (8:1) gearbox or as two ODDRX2 (4:1) gearboxes. Table 2-10 shows the gearbox signals. Table 2-10. Output Gearbox Signal List The gearboxes have three stage pipeline registers. The first stage registers sample the low-speed input data on the low-speed system clock. The second stage registers transfer data from the low-speed clock registers to the high- speed clock registers. The third stage pipeline registers controlled by high-speed edge clock shift and mux the high-speed data out to the sysIO buffer. Figure 2-17 shows the output gearbox block diagram. Name I/O Type Description Q Output High-speed data output D[7:0] Input Low-speed data from device core Video TX(7:1): D[6:0] GDDRX4(8:1): D[7:0] GDDRX2(4:1)(IOL-A): D[3:0] GDDRX2(4:1)(IOL-C): D[7:4] SCLK Input Slow-speed system clock ECLK [1:0] Input High-speed edge clock RST Input Reset |
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