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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LCMXO2-640ZE-3TG100C датащи(PDF) 20 Page - Lattice Semiconductor |
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LCMXO2-640ZE-3TG100C датащи(HTML) 20 Page - Lattice Semiconductor |
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20 / 106 page  2-16 Architecture MachXO2 Family Data Sheet Figure 2-12. MachXO2 Input Register Block Diagram (PIO on Left, Top and Bottom Edges) Right Edge The input register block on the right edge is a superset of the same block on the top, bottom, and left edges. In addition to the modes described above, the input register block on the right edge also supports DDR memory mode. In DDR memory mode, two registers are used to sample the data on the positive and negative edges of the modi- fied DQS (DQSR90) in the DDR Memory mode creating two data streams. Before entering the core, these two data streams are synchronized to the system clock to generate two data streams. The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade- quate timing when data is transferred to the system clock domain from the DQS domain. The DQSR90 and DDRCLKPOL signals are generated in the DQS read-write block. Figure 2-13. MachXO2 Input Register Block Diagram (PIO on Right Edge) Output Register Block The output register block registers signals from the core of the device before they are passed to the sysIO buffers. Left, Top, Bottom Edges In SDR mode, D0 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured as a D-type register or latch. SCLK INCK Q1 Q0 INDD D Q0 Q1 D Q Programmable Delay Cell D/L Q D Q D Q Q1 Q0 INDD D DQSR90 Q0 Q1 SCLK S0 S1 DDRCLKPOL Programmable Delay Cell D/L Q INCK D Q D Q D Q D Q D Q D Q D Q |
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