LCMXO2-640ZE-3TG100C datasheet(35/106 Pages) LATTICE

35 / 106 page

2-31

Architecture

MachXO2 Family Data Sheet

• Supports the following modes of operation:

– Watchdog timer

– Clear timer on compare match

–Fast PWM

– Phase and Frequency Correct PWM

• Programmable clock input source

• Programmable input clock prescaler

• One static interrupt output to routing

• One wake-up interrupt to on-chip standby mode controller.

• Three independent interrupt sources: overflow, output compare match, and input capture

• Auto reload

• Time-stamping support on the input capture unit

• Waveform generation on the output

• Glitch-free PWM waveform generation with variable PWM period

• Internal WISHBONE bus access to the control and status registers

• Stand-alone mode with preloaded control registers and direct reset input

Figure 2-23. Timer/Counter Block Diagram

Table 2-17. Timer/Counter Signal Description

For more details on these embedded functions, please refer to TN1205, Using User Flash Memory and Hardened

Control Functions in MachXO2 Devices.

Port

I/O

Description

tc_clki

Timer/Counter input clock signal

tc_rstn

tc_ic

Input capture trigger event, applicable for non-pwm modes with WISHBONE interface. If

enabled, a rising edge of this signal will be detected and synchronized to capture tc_cnt value

into tc_icr for time-stamping.

tc_int

Without WISHBONE – Can be used as overflow flag

With WISHBONE – Controlled by three IRQ registers

tc_oc

Timer counter output signal

EFB

Timer/Counter

Core

Logic

Routing

PWM

EFB

WISHBONE

Interface

Timer/

Counter

Registers

Control

Logic

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