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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LCMXO2-640ZE-3TG100C датащи(PDF) 60 Page - Lattice Semiconductor |
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LCMXO2-640ZE-3TG100C датащи(HTML) 60 Page - Lattice Semiconductor |
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60 / 106 page  3-21 DC and Switching Characteristics MachXO2 Family Data Sheet Generic DDRX2 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX2_TX.ECLK.Centered 9 tDVB Output Data Valid Before CLK Output MachXO2-640U, MachXO2-1200/U and larger devices, top side only 0.535 — 0.670 — 0.830 — ns tDVA Output Data Valid After CLK Output 0.535 — 0.670 — 0.830 — ns fDATA DDRX2 Serial Output Data Speed — 664 — 554 — 462 Mbps fDDRX2 DDRX2 ECLK Frequency (minimum limited by PLL) — 332 — 277 — 231 MHz fSCLK SCLK Frequency — 166 — 139 — 116 MHz Generic DDRX4 Outputs with Clock and Data Aligned at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Aligned 9 tDIA Output Data Invalid After CLK Output MachXO2-640U, MachXO2-1200/U and larger devices, top side only — 0.200 — 0.215 — 0.230 ns tDIB Output Data Invalid Before CLK Output — 0.200 — 0.215 — 0.230 ns fDATA DDRX4 Serial Output Data Speed — 756 — 630 — 524 Mbps fDDRX4 DDRX4 ECLK Frequency — 378 — 315 — 262 MHz fSCLK SCLK Frequency — 95 — 79 — 66 MHz Generic DDRX4 Outputs with Clock and Data Centered at Pin Using PCLK Pin for Clock Input – GDDRX4_TX.ECLK.Centered 9 tDVB Output Data Valid Before CLK Output MachXO2-640U, MachXO2-1200/U and larger devices, top side only 0.455 — 0.570 — 0.710 — ns tDVA Output Data Valid After CLK Output 0.455 — 0.570 — 0.710 — ns fDATA DDRX4 Serial Output Data Speed — 756 — 630 — 524 Mbps fDDRX4 DDRX4 ECLK Frequency (minimum limited by PLL) — 378 — 315 — 262 MHz fSCLK SCLK Frequency — 95 — 79 — 66 MHz 7:1 LVDS Outputs – GDDR71_TX.ECLK.7:1 9 tDVB Output Data Valid Before CLK Output MachXO2-640U, MachXO2-1200/U and larger devices, top side only. — 0.160 — 0.180 — 0.200 ns tDVA Output Data Valid After CLK Output — 0.160 — 0.180 — 0.200 ns fDATA DDR71 Serial Output Data Speed — 756 — 630 — 524 Mbps fDDR71 DDR71 ECLK Frequency — 378 — 315 — 262 MHz fCLKOUT 7:1 Output Clock Frequency (SCLK) (minimum limited by PLL) — 108 — 90 — 75 MHz Parameter Description Device -6 -5 -4 Units Min. Max. Min. Max. Min. Max. |
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