LCMXO2-640ZE-3TG100C datasheet(102/106 Pages) LATTICE

102 / 106 page

5-18

Ordering Information

MachXO2 Family Data Sheet

R1 Device Specifications

The LCMXO2-1200ZE/HC “R1” devices have the same specifications as their Standard (non-R1) counterparts

except as listed below. For more details on the R1 to Standard migration refer to AN8086, Designing for Migration

from MachXO2-1200-R1 to Standard Non-R1) Devices.

• The User Flash Memory (UFM) cannot be programmed through the internal WISHBONE interface. It can still be

programmed through the JTAG/SPI/I

2C ports.

• The on-chip differential input termination resistor value is higher than intended. It is approximately 200

 as

opposed to the intended 100

. It is recommended to use external termination resistors for differential inputs. The

on-chip termination resistors can be disabled through Lattice design software.

• Soft Error Detection logic may not produce the correct result when it is run for the first time after configuration. To

use this feature, discard the result from the first operation. Subsequent operations will produce the correct result.

• Under certain conditions, IIH exceeds data sheet specifications. The following table provides more details:

• The user SPI interface does not operate correctly in some situations. During master read access and slave write

access, the last byte received does not generate the RRDY interrupt.

• In GDDRX2, GDDRX4 and GDDR71 modes, ECLKSYNC may have a glitch in the output under certain condi-

tions, leading to possible loss of synchronization.

• When using the hard I

2C IP core, the I2C status registers I2C_1_SR and I2C_2_SR may not update correctly.

• PLL Lock signal will glitch high when coming out of standby. This glitch lasts for about 10µsec before returning

low.

• Dual boot only available on HC devices, requires tying VCC and VCCIO2 to the same 3.3V or 2.5V supply.

Condition

Clamp

Pad Rising

IIH Max.

Pad Falling

IIH Min.

Steady State Pad

High IIH

Steady State Pad

Low IIL

VPAD > VCCIO

OFF

1mA

-1mA

1mA

10µA

VPAD = VCCIO

10µA

-10µA

10µA

VPAD = VCCIO

OFF

1mA

-1mA

1mA

10µA

VPAD < VCCIO

OFF

10µA

-10µA

10µA

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