ADV7150LS85 datasheet(26/36 Pages) AD

26 / 36 page

ADV7150

–26–

REV. A

APPENDIX 1

BOARD DESIGN AND LAYOUT CONSIDERATIONS

REF

SET

IOR

IOG

IOB

PLL

GND

COMP

IOR

IOG

IOB

SET

280

Ω

(1% METAL)

AD589

(1.2V REF)

0.1

µF

+5V (V

AA )

Ω

COMPLIMENTARY

OUTPUTS

CO-AXIAL CABLE

(75

Ω)

BNC

CONNECTORS

MONITOR

(CRT)

+5V (V

AA )

0.1

µF

ANALOG POWER PLANE

µF

0.1

µF

0.01

µF

0.1

µF

0.01

µF

0.1

µF

0.01

µF

0.1

µF

0.01

µF

+5V (V

AA )

0.1

µF

+5V (V

CC )

(FERRITE BEAD)

NOTES:

1. ALL RESISTORS ARE 1% METAL FILM

2. 0.1

µF AND 0.01µF CAPACITORS ARE CERAMIC

3. ADDITIONAL DIGITALCIRCUITRY OMITTED FOR CLARITY

ADV7150

POWER SUPPLY DECOUPLING (0.1

µF AND 0.01µF CAPACITOR FOR EACH V

AA GROUP)

Recommended Analog Circuit Layout

power plane (VCC) at a single point through a ferrite bead. This

bead should be located within three inches of the ADV7150.

The PCB power plane should provide power to all digital logic

on the PC board, and the analog power plane should provide

power to all ADV7150 power pins and voltage reference circuitry.

Plane-to-plane noise coupling can be reduced by ensuring that

portions of the regular PCB power and ground planes do not

overlay portions of the analog power plane, unless they can be

arranged such that the plane-to-plane noise is common mode.

Supply Decoupling

For optimum performance, bypass capacitors should be installed

using the shortest leads possible, consistent with reliable opera-

tion, to reduce the lead inductance. Best performance is obtained

with 0.1

µF ceramic capacitor decoupling. Each group of V

pins on the ADV7150 must have at least one 0.1

µF decoupling

capacitor to GND. These capacitors should be placed as close

as possible to the device.

It is important to note that while the ADV7150 contains cir-

cuitry to reject power supply noise, this rejection decreases with

frequency. If a high frequency switching power supply is used,

the designer should pay close attention to reducing power sup-

ply noise and consider using a three terminal voltage regulator

for supplying power to the analog power plane.

The ADV7150 is a highly integrated circuit containing both

precision analog and high speed digital circuitry. It has been

designed to minimize interference effects on the integrity of the

analog circuitry by the high speed digital circuitry. It is impera-

tive that these same design and layout techniques be applied to

the system level design such that high speed, accurate perfor-

mance is achieved. The “Recommended Analog Circuit Layout”

shows the analog interface between the device and monitor.

The layout should be optimized for lowest noise on the ADV7150

power and ground lines by shielding the digital inputs and pro-

viding good decoupling. The lead length between groups of VAA

and GND pins should by minimized so as to minimize inductive

ringing.

Ground Planes

The ground plane should encompass all ADV7150 ground pins,

voltage reference circuitry, power supply bypass circuitry for the

ADV7150, the analog output traces, and all the digital signal

traces leading up to the ADV7150. The ground plane is the

graphics board’s common ground plane.

Power Planes

The ADV7150 and any associated analog circuitry should have

its own power plane, referred to as the analog power plane (VAA).

This power plane should be connected to the regular PCB

ADV7150LS85 датащи(PDF) 26 Page - Analog Devices

ADV7150LS85 датащи(HTML) 26 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

датащи скачать

ссылки URL