ADV7150LS85 datasheet(18/36 Pages) AD

18 / 36 page

ADV7150

–18–

REV. A

MPU PORT

D9 – D0

10 (8+2)

ADDR

(A7–A0)

REVISION

COMMAND

REGISTERS

(CR1–CR3)

TEST

REGISTERS

(MR1)

DATA TO

PALETTES

CONTROL REGISTERS

COLOR REGISTERS

ADDRESS

MODE

BLUE

PIXEL MASK

R/W

GREEN

RED

Figure 27. MPU Port and Register Configuration

Data is read from the color palette by first writing to the address

forms three successive read cycles from each of the red, green

and blue locations (10-bit or 8-bit) of the RAM. An internal

pointer moves from red to green to blue after each read is com-

pleted. This pointer is reset to red after a blue read or whenever

the address register is written. The address register then auto-

matically increments to point to the next RAM location, and a

similar red, green and blue palette read sequence is performed.

The address register resets to 00H following a blue read cycle of

color palette RAM location FFH.

The MPU can write to or read from all of the ADV7150s regis-

ters. C0 and C1 determine whether the Mode Register or Ad-

dress Register is being accessed. Access to these registers is

direct. The Control Registers are accessed indirectly. The

Address Register must point to the desired Control Register.

Figure 28 along with the 8-bit and 10-bit Interface Truth Tables

illustrate the structure and protocol for device communication

over the MPU port.

MODE REGISTER

(MR17–MR10)

ADDRESS REGISTER

(A7–A0)

ADDRESS

(A15–A0)

CONTROL

REGISTERS

00H

01H

02H

PIXEL TEST REGISTER

DAC TEST REGISTER

* THIS REGISTER IS READ ONLY.

A READ CYCLE WILL RETURN ZEROS "00".

LOOK-UP TABLE RAM

(256 x 30)

RED

(R9–R0)

GREEN

(G9–G0)

BLUE

(B9–B0)

POINTS TO LOCATION

CORRESPONDING TO

ADDRESS REG (A7–A0)

ADDRESS REG = ADDRESS REG + 1

C1 = 1

C0 = 0

C1 = 0

C0 = 1

C1 = 1

C0 = 1

C1 = 0

C0 = 0

SYNC, BLANK & I

PLL

TEST REGISTER

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

RESERVED* (READ ONLY)

REVISION REGISTER

ID REGISTER (READ ONLY)

PIXEL MASK REGISTER

COMMAND REGISTER 1

COMMAND REGISTER 2

COMMAND REGISTER 3

Figure 28. Internal Register Configuration and Address Decoding

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