ADV7150LS85 datasheet(20/36 Pages) AD

20 / 36 page

ADV7150

–20–

REV. A

Power-On Reset

On power-up of the ADV7150 executes a power-on reset opera-

tion. This initializes the pixel port such that the pixel sequence

ABCD starts at A. The Mode Register (MR17–MR10), Com-

mand Register 2 (CR27–CR20) and Command Register 3

(CR37–CR30) have all bits set to a Logic “1.” Command Regis-

ter 1 (CR17–CR10) has all bits set to a Logic “0.”

The output clocking signals are also set during this reset period.

PRGCKOUT = CLOCK/32

LOADOUT = CLOCK/4

The power-on reset is activated when VAA goes from 0 V to

5 V. This reset is active for 1

µs. The ADV7150 should not be

accessed during this reset period. The pixel clock should be

applied at power-up.

The following section describes each register, including Address

in terms of its configuration.

Address Register (A7–A0)

As illustrated in the previous tables, the C0 and C1 control in-

puts, in conjunction with this address register specify which

control register, or color palette location is accessed by the

MPU port. The address register is 8-bits wide and can be read

from as well as written to. When writing to or reading from the

color palette on a sequential basis, only the start address needs

to be written. After a red, green and blue write sequence, the

address register is automatically incremented.

MODE REGISTER MR1 (MR19–MR10)

The mode register is a 10-bit wide register. However for pro-

gramming purposes, it may be considered as an 8-bit wide regis-

ter (MR18 and MR19 are both reserved). It is denoted as

MR17–MR10 for simplification purposes.

The diagram shows the various operations under the control of

the mode register. This register can be read from as well written

to. In read mode, if MR18 and MR19 are read back, they are

both returned as zeros.

Mode Register (MR17–MR10) Bit Description

Reset Control (MR10)

This bit is used to reset the pixel port sampling sequence. This

ensures that the pixel sequence ABCD starts at A. It is reset by

writing a “1” followed by a “0” followed by a “1.” This bit must

be run through this cycle during the initialization sequence.

RAM-DAC Resolution Control (MR11)

When this is programmed with a “1,” the RAM is 30 bits deep

(10 bits each for red, green and blue) and each of the three

DACs is configured for 10-bit resolution. When MR11 is

programmed with a “0,” the RAM is 24-bits deep (8 bits each

for red, green and blue) and the DACs are configured for 8-bit

resolution. The two LSBs of the 10-bit DACs are pulled down

to zero in 8-bit RAM-DAC mode.

MPU Databus Width (MR12)

This bit determines the width of the MPU port. It is configured

as either a 10-bit wide (D9–D0) or 8-bit wide (D7–D0) bus.

10-bit data can be written to the device when configured in

8-bit wide mode. The 8 MSBs are first written on D7–D0, then

the two LSBs are written over D1–D0. Bits D9–D8 are zeros in

8-bit mode.

Operational Mode Control (MR14–MR13)

When MR14 is “0” and MR13 is “1,” the part operates in

normal mode.

Calibrate LOADIN (MR15)

This bit automatically calibrates the onboard LOADIN/

LOADOUT synchronization circuit. A “0” to “1” transition

initiates calibration. This bit is set to “0” in normal operation.

See “Pipeline Delay and Calibration” section. This bit must be

run through this cycle during the initialization sequence.

MR17

MR16

* THESE BITS ARE READ-ONLY RESERVED BITS.

A READ CYCLE WILL RETURN ZEROS "00."

RESERVED*

MR16

PS0

MR17

PS1

PALETTE SELECT

MATCH BITS CONTROL

RAM-DAC

RESOLUTION CONTROL

8-BIT

10-BIT

MR11

MPU DATA BUS WIDTH

8-BIT (D7–D0)

10-BIT (D9–D0)

MR12

CALIBRATE

LOADIN

MR15

RESET CONTROL

MR10

OPERATIONAL MODE CONTROL

RESERVED

NORMAL OPERATION

RESERVED

MR14

MR13

MR19

MR18

MR15

MR14

MR13

MR12

MR11

MR10

Mode Register 1 (MR1) (MR19–MR10)

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