поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

ADV7150LS85 датащи(PDF) 22 Page - Analog Devices

номер детали ADV7150LS85
подробное описание детали  CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC
PDF  36 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

ADV7150LS85 датащи(HTML) 22 Page - Analog Devices

Back Button ADV7150LS85 Datasheet HTML 18Page - Analog Devices ADV7150LS85 Datasheet HTML 19Page - Analog Devices ADV7150LS85 Datasheet HTML 20Page - Analog Devices ADV7150LS85 Datasheet HTML 21Page - Analog Devices ADV7150LS85 Datasheet HTML 22Page - Analog Devices ADV7150LS85 Datasheet HTML 23Page - Analog Devices ADV7150LS85 Datasheet HTML 24Page - Analog Devices ADV7150LS85 Datasheet HTML 25Page - Analog Devices ADV7150LS85 Datasheet HTML 26Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 22 / 36 page
background image
ADV7150
–22–
REV. A
COMMAND REGISTER 2 (CR2)
(Address Reg (A7–A0) = 06H)
This register contains a number of control bits as shown in the
diagram. CR2 is a 10-bit wide register. However, for program-
ming purposes, it may be considered as an 8-bit wide register
(CR28 and CR29 are both reserved).
The diagram shows the various operations under the control of
CR2. This register can be read from as well written to. In read
mode, CR28 and CR29 are both returned as zeros.
COMMAND REGISTER 2-BIT DESCRIPTION
R7 Trigger Polarity Control (CR20)
This bit is used when the device is in test/diagnostic mode. It
determines whether the pixel data is latched into the test regis-
ters in the rising or falling edge of R7. (See “Test Diagnostics”
section.)
IPLL Trigger Control (CR21)
This bit specifies whether the IPLL output is triggered from
BLANK
or SYNC.
SYNC
Recognition Control (CR22)
This bit specifies whether the video SYNC input is to be
encoded onto the IOG analog output or ignored.
Pedestal Enable Control (CR23)
This bit specifies whether a 0 IRE or a 7.5 IRE blanking pedes-
tal is to be generated on the video outputs.
True-Color/Pseudo-Color Mode Control (CR27–CR24)
These 4 bits specify the various color modes. These include a
24-bit true-color mode, two 15-bit true-color modes and three
8-bit pseudo color modes.
CR20
RESERVED*
CR26
CR25
CR24
CR27
0
1
CR21
I
PLL TRIGGER CONTROL
SYNC
BLANK
R7 TRIGGER
POLARITY CONTROL
0
1
CR20
CR29
CR28
CR22
0
IGNORE
1
DECODE
SYNC RECOGNITION
CONTROL
*THESE BITS ARE READ-
ONLY RESERVED BITS.
A READ CYCLE WILL
RETURN ZEROS "00."
CR21
CR23
CR22
TRUE COLOR/PSEUDO-COLOR MODE CONTROL
MODE
0
1
1
1
10
00
1
00
0
11
0
1
CR27
CR26
CR24
CR25
11
0
0
0
0
00
8-BIT PSEUDO COLOR ON R7–R0
8-BIT PSEUDO COLOR ON G7–G0
8-BIT PSEUDO COLOR ON B7–B0
15-BIT TRUE COLOR ON
R7–R3, G7–G3, B7–B3
15-BIT TRUE COLOR ON
R7–R0, G6–G0
24-BIT TRUE COLOR
R7–R0, G7–G0, B7–B0
PEDESTAL ENABLE
CONTROL
CR23
0
0 IRE
1
7.5 IRE
Command Register 2 (CR2) (CR29–CR20)



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com