ADMC401BST datasheet(34/60 Pages) AD

34 / 60 page

REV. B

ADMC401

–34–

On the occurrence of a PWM shutdown command (either from

the

PWMTRIP pin, the PIO lines or the PWMSWT register),

a PWMTRIP interrupt will be generated. In addition, the

PWMSYNC pulse no longer appears at the output pin. How-

ever, internal operation of the PWM timer continues. Following

a PWM shutdown, the PWM can only be re-enabled (in a

PWMTRIP interrupt service routine, for example) by writing to

all of the PWMTM, PWMCHA, PWMCHB and PWMCHC

registers. Provided the external fault has been cleared and the

PWMTRIP or appropriate PIO lines have returned to a HI

level, the PWM controller will restart.

PWM REGISTERS

The PWM registers are described in at the end of this data sheet.

The parameters of the PWM block for operation at 26 MHz are

tabulated in Table V.

ENCODER INTERFACE UNIT

OVERVIEW OF ENCODER INTERFACE UNIT

The ADMC401 incorporates a powerful encoder interface to

incremental shaft encoders, that are often used for position

feedback in high performance motion control systems. The

functional block diagram of the entire encoder interface system

of the ADMC401 is shown in Figure 28.

The encoder interface unit (EIU) includes a 16-bit quadrature

up/down counter, programmable input noise filtering of the

encoder input signals and the zero markers, and has four dedi-

cated pins on the ADMC401. The quadrature encoder signals

(or alternatively, frequency and direction inputs) are applied at

the EIA and EIB pins. In addition, two zero marker/strobe in-

puts are provided on pins EIZ and EIS. These inputs may be

used to latch the contents of the encoder quadrature counter

into dedicated registers, EIZLATCH and EISLATCH, on the

occurrence of external events at the EIZ and EIS pins. These

events may be programmed to be either rising edge only (latch

event) or rising edge if the encoder is moving in the forward

direction and falling edge if the encoder is moving in the reverse

direction (software latched zero marker functionality). The

encoder interface unit incorporates programmable noise filtering

on the four encoder inputs to prevent spurious noise pulses from

adversely affecting the operation of the quadrature counter. The

encoder interface unit operates at a clock frequency equal to the

DSP instruction rate. The encoder interface unit operates correctly

with encoder signals at frequencies of up to 4.33 MHz, corre-

sponding to a maximum quadrature frequency of 17.3 MHz

(assuming an ideal quadrature relationship between the input

EIA and EIB signals).

EETCNT(15…0)

EIUCNT(15…0)

EIUMAXCNT(15…0)

EIUCTRL(8…0)

EIUSTAT(7…0)

EISLATCH(15…0)

EIZLATCH(15…0)

EIUFILTER(5…0)

PULSE

DECIMATOR

CLOCK DIVIDER

ENCODER EVENT

TIMER

QUADRATURE SIGNAL

ENCODER INTERFACE BLOCK

ENCODER LOOP TIMER

TIMEOUT

DIRECTION

ENCODER EVENT

TIMER BLOCK

EETDIV(15…0)

EETSTAT(0)

EETT(15…0)

EETDELTAT(15…0)

EETN(7…0)

EIUSCALE (7…0)

EIUTIMER (15…0)

EIUPERIOD (15…0)

EIA

16-BIT

QUADRATURE

UP/DOWN

COUNTER

ENCODER

COUNTER

CONTROL

EIB

EIZ

EIS

PROGRAMMABLE

NOISE FILTERS

Figure 28. Configuration of Encoder Interface System of

ADMC401

The EIU may be programmed to use the zero marker on EIZ to

reset the quadrature encoder in hardware, if required. Alterna-

tively, the zero marker can be ignored and the encoder quadra-

ture counter is reset according to the contents of a maximum

count register, EIUMAXCNT. There is also a “single north

marker” mode available in which the encoder quadrature

counter is reset only on the first zero marker pulse. Both modes

are enabled by dedicated control bits in the EIU control regis-

ter, EIUCTRL. A status bit is set in the EIUSTAT register on

the first occurrence of the zero marker.

The encoder interface unit can also be made to implement some

error checking functions. If the error checking mode is enabled,

upon the occurrence of a zero pulse, the contents of the encoder

counter register are compared with the expected value (0 or

EIUMAXCNT depending on the direction of rotation). If an

encoder count error is detected, a status bit in the EIUSTAT

Table V. Fundamental Characteristics of PWM Generation Unit of ADMC401 (CLKOUT = 26 MHz)

Parameter

Test Conditions

Min

Typ

Max

Unit

Counter Resolution

Bits

Edge Resolution

Double Update Mode

38.5

Programmable Dead Time

78.8

µs

Dead Time Increments

77.0

TMIN

Programmable Minimum Pulsewidth

39.4

µs

Minimum Pulsewidth Increments

38.5

fPWM

PWM Switching Frequency

16-Bit Resolution

198

fPWM

PWM Switching Frequency

8-Bit Resolution

102

kHz

TPWMSYNC PWMSYNC Pulsewidth

38.5

9850

PWMSYNC Pulsewidth Increments

38.5

fCHOP

Gate Drive Chopping Frequency

25.4

6500

kHz

NOTE: Higher switching frequencies are possible at reduced resolutions (i.e., 202.8 kHz at 7 bits, 405.6 kHz at 6 bits, etc.)

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