ADMC401BST datasheet(5/60 Pages) AD

номер детали	ADMC401BST

подробное описание детали	Single-Chip, DSP-Based High Performance Motor Controller

PDF	60 Pages

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производитель	AD [Analog Devices]

домашняя страница	http://www.analog.com

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ADMC401

–5–

REV. B

Parameter

Min

Max

Unit

Clock Signals

CK is defined as 0.5tCKI. The ADMC401 uses an input clock

with a frequency equal to half the instruction rate; a 13 MHz

clock (which is equivalent to 76.9 ns) yields a 38.5 ns processor

cycle (equivalent to 26 MHz). t

CK values within the range of

0.5t

CKI period should be substituted for all relevant timing

parameters to obtain specification value.

Example: t

CKH = 0.5tCK – 10 ns = 0.5 (38.5 ns) – 10 ns = 9.25 ns.

Timing Requirements:

CKI

CLKIN Period

76.9

150

CKIL

CLKIN Width Low

CKIH

CLKIN Width High

Switching Characteristics:

CKL

CLKOUT Width Low

0.5t

CK – 10

CKH

CLKOUT Width High

0.5t

CK – 10

CKOH

CLKIN High to CLKOUT High

Control Signals

Timing Requirement:

RSP

RESET Width Low

PWM Shutdown Signals

Timing Requirements:

tPWMTPW

PWMTRIP Width Low

tCK

tPIOPWM

PIO Width Low

2tCK

ADC Signals

Timing Requirements:

tCSI

Internal Convert Start Width High

2tCK

tCSE

External Convert Start Width High

2tCK

NOTE

1Applies after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles assuming stable CLKIN (not including crystal

oscillator start-up time).

CLKIN

CLKOUT

tCKOH

tCKI

tCKIH

tCKIL

tCKH

tCKL

Figure 1. Clock Signals

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