ADMC401BST datasheet(26/60 Pages) AD

26 / 60 page

REV. B

ADMC401

–26–

ADC6 is valid and Bit 3 is set when the data in ADC3 and

ADC7 is valid. At the start of the next conversion sequence, all

bits of the ADCSTAT register are cleared. Additionally, at the

end of the complete conversion sequence (when the data in the

ADC7 register is valid), a dedicated ADC interrupt is generated.

This interrupt can be masked and controlled by the PIC block.

Depending on initial synchronization delays, the worst case total

conversion time (defined as the duration from the rising edge of

the convert start command to the generation of the ADC inter-

rupt) for all eight channels is:

tCONV = 49

× tCK

which corresponds to 1.88

µs for a DSP instruction rate of

26 MHz. Additionally, in this operating mode, the time delay

between sampling of successive pairs of analog inputs is 8tCK or

308 ns (at 26 MHz).

Sequential Sampling Mode

This operating mode is selected by setting Bit 3 and clearing

Bit 4 of the ADCCTRL register. In this operating mode, simul-

taneous sampling is abandoned and the A/D conversion se-

quence samples each analog input sequentially. Therefore, in

the first ADC clock period, VIN0 is sampled and held by the

first sample and hold amplifier. In the second clock period, the

held sample of VIN0 is applied to the first stage of the ADC

pipeline and the VIN1 signal is sampled. This process continues

until each of the analog inputs has been sequentially sampled

and converted (i.e., VIN0 followed by VIN1 followed by VIN2,

etc.). In this operating mode, the total conversion time is the

same as the Simultaneous Sampling mode. However, successive

channels are sampled at 4tCK (or 154 ns at 26 MHz) intervals.

In this mode, Bits 0 to 3 of the ADCSTAT register are all set

together when all eight conversions are complete. The interrupt

is generated, as before, when the data in the ADC7 register is valid.

Offset Calibration Mode

In order to maintain the high accuracy of the ADC system of

the ADMC401, it may be necessary to measure and compensate

for any intrinsic offset and/or gain errors in the A/D conversion

system. The Offset Calibration mode, which is selected by setting

Bit 4 and clearing Bit 3 of the ADCCTRL register, is intended

to be used for measuring any offsets in the sample and hold

amplifiers. When this mode is selected, all analog inputs (VIN0

to VIN7, ASHAN and BSHAN) are disconnected from the

inputs to the sample and hold amplifiers, and the SHA inputs

are internally connected together and to the reference voltage

(at the VREF pin). Since these connections are in effect only

during the conversion sequence, a complete conversion se-

quence must be initiated. Following the end of conversion,

the data in the ADC0 to ADC3 registers may be taken as four

separate measurements of the offset of the first sample and hold

amplifier. Similarly, the data in the ADC4 to ADC7 registers

may be taken as measurements of the offset associated with the

second sample and hold amplifier. These data values could be

averaged to obtain an offset value for each sample and hold

amplifier that could be stored and used to compensate all future

measurements. The end of conversion status bits are updated

and the interrupt is generated in a manner identical to the Si-

multaneous Sampling mode.

Gain Calibration Mode

It may be desirable to measure and compensate for any gain

errors associated with the A/D conversion process across the

entire input voltage span of the A/D system. The Gain Calibra-

tion mode, selected by setting both Bits 3 and 4 of the ADCCTRL

mining the amount of gain compensation that may be required.

In this mode the dedicated GAIN input pin is internally con-

nected directly to the noninverting input of each sample and

hold amplifier. The user may apply different precise analog

voltages across the input voltage span to this pin to measure

gain errors over the operating range.

A complete conversion sequence for each different GAIN input

must be initiated. Following the end of conversion, the data in

the ADC0 to ADC3 registers may be used to calculate four

separate measurements of the gain error of the first sample and

hold amplifier. Similarly, the data in the ADC4 to ADC7 regis-

ters may be used to calculate the gain associated with the second

sample and hold amplifier. These data values could be averaged

to obtain gain error values for each sample and hold amplifier

that could be stored and used to compensate all future measure-

ments. The end of conversion status bits are updated and the

interrupt is generated in a manner identical to the Simulta-

neous Sampling mode.

ADCXTRA REGISTER

Following the end of conversion sequence in any of the four

operating modes, the A/D system reverts to its Single Channel

mode. In this configuration, the multiplexers are set such that

the VIN0 input is continuously sampled and converted. The results

of these conversions are placed in the dedicated ADCXTRA

every ADC clock period (or 154 ns at 26 MHz). This feature

permits the continuous tracking of a single analog input, if re-

quired. The OTR bit for these conversions is placed in Bit 4 of

the ADCSTAT register. No interrupt is generated following

these conversions and no other status bits are generated. The

ADCXTRA register is not updated during the conversion se-

quence of any of the four operating modes.

VOLTAGE REFERENCE OPERATION

The ADMC401 contains an onboard bandgap reference that

can be used to provide a precise 2.0 V output for use by the A/D

system and externally on the VREF pin for biasing and level–

shifting functions. Additionally, the ADMC401 may be config-

ured to operate with an external reference applied to the VREF

pin. The SENSE pin is used to select between internal and

external references.

The actual reference voltages used by the internal ADC circuitry

of the ADMC401 appear on the CAPT and CAPB pins. For

correct operation of the internal voltage reference generation

circuitry, either with internal or external reference, it is neces-

sary to add a capacitor network between these pins, as shown in

Figure 20. A 10

µF tantalum capacitor in parallel with a 0.1 µF

ceramic is recommended as well as two 0.1

µF capacitors to

analog ground. The internal bias circuitry may take up to 15 ms

after power-up to settle. Any ADC conversions performed prior

to this may not be as accurate as possible. The start-up time

may be evaluated by measuring how long it takes for the voltage

difference between CAPT and CAPB to settle to VREF. Addi-

tionally, a 0.1

µF ceramic capacitor must be connected between

the CML pin and analog ground. Finally, the VREF pin should

be decoupled to analog ground by a 10

µF tantalum capacitor in

parallel with a 0.1

µF ceramic capacitor.

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